# New instructions for CR/INT predication
+**DRAFT STATUS**
+
See:
* main bugreport for crweirds
# Instruction form and pseudocode
-Instruction format:
+**DRAFT** Instruction format (use of MAJOR 19 not approved by
+OPF ISA WG):
|0-5|6-10 |11|12-15|16-18|19-20|21-25 |26-30 |31|name |
|---|---- |--|-----|-----|-----|----- |----- |--|---- |
-|19 |RT | |mask |BB | |XO[0:4]|XO[5:9]|/ | |
-|19 |RT |M |mask |BB | 0 0 |XO[0:4]|0 mode |Rc|crrweird |
-|19 |RA |/ |mask |BT | 0 1 |XO[0:4]|0 mode |/ |mtcrweird |
-|19 |BT //|M |mask |BB | 1 0 |XO[0:4]|0 mode |/ |crweird |
-|19 |BFT |/ |mask |BB | 1 1 |XO[0:4]|0 mode |/ |crweirder |
+|19 |RT | |mask |BFA | |XO[0:4]|XO[5:9]|/ | |
+|19 |RT |M |mask |BFA | 0 0 |XO[0:4]|0 mode |Rc|crrweird |
+|19 |RA |M |mask |BF | 0 1 |XO[0:4]|0 mode |/ |mtcrweird |
+|19 |BFT//|M |mask |BFA | 1 0 |XO[0:4]|0 mode |/ |crweirder |
+|19 |BF |M |mask |BFA | 1 1 |XO[0:4]|0 mode |/ |crweird |
**crrweird**
bit 19=0, bit 20=0
- crrweird: RT, BB, mask.mode
+ crrweird: RT, BFA, M, mask.mode
- creg = CR{BB}
+ creg = CR{BFA}
n0 = mask[0] & (mode[0] == creg[0])
n1 = mask[1] & (mode[1] == creg[1])
n2 = mask[2] & (mode[2] == creg[2])
bit 19=0, bit 20=1
- mtcrweird: BT, RA, mask.mode
+ mtcrweird: BF, RA, M, mask.mode
reg = (RA|0)
lsb = reg[63] # MSB0 numbering
n1 = mask[1] & (mode[1] == lsb)
n2 = mask[2] & (mode[2] == lsb)
n3 = mask[3] & (mode[3] == lsb)
- CR{BT} = n0 || n1 || n2 || n3
+ result = n0 || n1 || n2 || n3
+ if M:
+ result |= CR{BF} & ~mask
+ CR{BF} = result
+
+Note that when M=1 this operation is a Read-Modify-Write on the CR Field
+BF. Masked-out bits of the 4-bit CR Field BF will not be changed when
+M=1. Correspondingly when M=0 this operation is an overwrite: no read
+of BF is required because the masked-out bits of the BF CR Field are
+set to zero.
When used with SVP64 Prefixing this is a [[openpower/sv/cr_ops]] SVP64 type operation that has
3-bit Data-dependent and 3-bit Predicate-result capability
-(BT is 3 bits)
+(BF is 3 bits)
**crweird**
bit 19=1, bit 20=0
- crweird: BT, BB, mask.mode
+ crweird: BF, BFA, M, mask.mode
- creg = CR{BB}
+ creg = CR{BFA}
n0 = mask[0] & (mode[0] == creg[0])
n1 = mask[1] & (mode[1] == creg[1])
n2 = mask[2] & (mode[2] == creg[2])
n3 = mask[3] & (mode[3] == creg[3])
- CR{BT} = n0 || n1 || n2 || n3
+ result = n0 || n1 || n2 || n3
+ if M:
+ result |= CR{BF} & ~mask
+ CR{BF} = result
+
+Note that when M=1 this operation is a Read-Modify-Write on the CR Field
+BF. Masked-out bits of the 4-bit CR Field BF will not be changed when
+M=1. Correspondingly when M=0 this operation is an overwrite: no read
+of BF is required because the masked-out bits of the BF CR Field are
+set to zero.
When used with SVP64 Prefixing this is a [[openpower/sv/cr_ops]] SVP64 type operation that has
3-bit Data-dependent and 3-bit Predicate-result capability
-(BT is 3 bits)
+(BF is 3 bits)
**crweirder**
bit 19=1, bit 20=1
- crweirder: BFT, BB, mask.mode
+ crweirder: BT, BFA, mask.mode
- creg = CR{BB}
+ creg = CR{BFA}
n0 = mask[0] & (mode[0] == creg[0])
n1 = mask[1] & (mode[1] == creg[1])
n2 = mask[2] & (mode[2] == creg[2])
n3 = mask[3] & (mode[3] == creg[3])
- BF = BFT[2:4] # select CR
- bit = BFT[0:1] # select bit of CR
+ BF = BT[2:4] # select CR
+ bit = BT[0:1] # select bit of CR
result = n0|n1|n2|n3 if M else n0&n1&n2&n3
CR{BF}[bit] = result
**Example Pseudo-ops:**
- mtcri BB, mode mtcrweird r0, BB, 0b1111.~mode
- mtcrset BB, mask mtcrweird r0, BB, mask.0b0000
- mtcrclr BB, mask mtcrweird r0, BB, mask.0b1111
+ mtcri BF, mode mtcrweird BF, r0, 0, 0b1111.~mode
+ mtcrset BF, mask mtcrweird BF, r0, 1, mask.0b0000
+ mtcrclr BF, mask mtcrweird BF, r0, 1, mask.0b1111
# Vectorised versions
Instead however in the scalar case these instructions **remain in the same register** and insert or transfer between **bits** of the scalar integer source or destination.
Further useful violation of the normal SV Elwidth override rules allows
-for packing of multiple CR test results into an Integer Element. Note
+for packing (or unpacking) of multiple CR test results into
+(or out of) an Integer Element. Note
that the CR (source operand) elwidth field is utilised to determine the bit-
packing size (1/2/4/8 with remaining bits within the Integer element
set to zero) whilst the INT (dest operand) elwidth field still sets
* in the scalar case the CR-Vector assessment
is stored bit-wise starting at the LSB of the
destination scalar INT
-* in the INT-vector case the result is stored in the
- LSB of each element in the result vector
-
-Note that element width overrides are respected on the INT src or destination register, however that it is the CR element-width
-override that is used to indicate how many bits of CR results
-are packed/extracted into/from each INT register
+* in the INT-vector case the results are packed into LSBs
+ of the INT Elements, the packing arrangement depending on both
+ elwidth override settings.
# v3.1 setbc instructions
projects / libreriscv.git / blobdiff