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[libreriscv.git] / openpower / sv / cr_int_predication.mdwn

diff --git a/openpower/sv/cr_int_predication.mdwn b/openpower/sv/cr_int_predication.mdwn
index 6d3708f682f2ee4acb046ba89cc654d150a9529b..c30776ef32544e534c19b2a63ecc04e52a6d7372 100644 (file)
--- a/openpower/sv/cr_int_predication.mdwn
+++ b/openpower/sv/cr_int_predication.mdwn
@@ -60,21 +60,18 @@ Purpose:
 * To provide a vectorised version of the same, suitable for advanced
   predication
 
-Side-effects:
+Useful side-effects:
 
-* mtcrweird when RA=0 is a means to set or clear arbitrary CR bits
+* mtcrweird when RA=0 is a means to set or clear 
+  multiple arbitrary CR Field bits simultaneously,
   using immediates embedded within the instruction.
-
-(Twin) Predication interactions:
-
-* INT twin predication with zeroing is a way to copy an integer into
-  CRs without necessarily needing the INT register (RA).  if it is, it is
-  effectively ANDed (or negate-and-ANDed) with the INT Predicate
-* CR twin predication with zeroing is likewise a way to interact with
-  the incoming integer
-
-this gets particularly powerful if data-dependent predication is also
-enabled.  further explanation is below.
+* With SVP64 on the weird instructions there is bit-for-bit interaction
+  between GPR predicate masks (r3, r10, r31) and the source
+  or destination GPR, in ways that are not possible with other
+  SVP64 instructions because normal SVP64 is bit-per-element.
+  On these weird instructions the element in effect *is* a bit.
+* `mfcrweird` mitigates a need to add `conflictd`, part of
+  [[sv/vector_ops]], as well as allowing more complex comparisons.
 
 # Bit ordering.
 
@@ -101,7 +98,7 @@ OPF ISA WG):
 
 mode is encoded in XO and is 4 bits
 
-    crrweird: RT, BFA, M, mask.mode
+    crrweird: RT,BFA,M,mask,mode
 
     creg = CR{BFA}
     n0 = mask[0] & (mode[0] == creg[0])
@@ -125,7 +122,7 @@ sequentially into the destination. *Destination elwidth overrides still apply*.
 
 mode is encoded in XO and is 4 bits
 
-    mfcrrweird: RT, BFA, mask.mode
+    mfcrrweird: RT,BFA,mask,mode
 
     creg = CR{BFA}
     n0 = mask[0] & (mode[0] == creg[0])
@@ -149,12 +146,13 @@ into the destination.  *Destination elwidth overrides still apply*
 
 mode is encoded in XO and is 4 bits
 
-    mtcrrweird: BF, RA, M, mask.mode
+    mtcrrweird: BF,RA,M,mask,mode
 
-    n0 = mask[0] & (mode[0] == RA[63])
-    n1 = mask[1] & (mode[1] == RA[62])
-    n2 = mask[2] & (mode[2] == RA[61])
-    n3 = mask[3] & (mode[3] == RA[60])
+    a = (RA|0)
+    n0 = mask[0] & (mode[0] == a[63])
+    n1 = mask[1] & (mode[1] == a[62])
+    n2 = mask[2] & (mode[2] == a[61])
+    n3 = mask[3] & (mode[3] == a[60])
     result = n0 || n1 || n2 || n3
     if M:
         result |= CR{BF} & ~mask
@@ -166,7 +164,7 @@ Mode capability
 
 **mtcrweird**
 
-    mtcrweird: BF, RA, M, mask.mode
+    mtcrweird: BF,RA,M,mask,mode
 
     reg = (RA|0)
     lsb = reg[63] # MSB0 numbering
@@ -199,7 +197,7 @@ Unlike `mcrf` the bits of the CR Field may not change position:
 the EQ bit from the source may only go into the EQ bit of the
 destination (optionally inverted, set, or cleared).
 
-    mcrfm: BF, BFA, M, mask.mode
+    mcrfm: BF,BFA,M,mask,mode
 
     result = mask & CR{BFA}
     if M:
@@ -207,7 +205,7 @@ destination (optionally inverted, set, or cleared).
     result ^= mode
     CR{BF} = result
 
-Note that when M=1 this operation is a Read-Modify-Write on the CR Field
+When M=1 this operation is a Read-Modify-Write on the CR Field
 BF. Masked-out bits of the 4-bit CR Field BF will not be changed when
 M=1. Correspondingly when M=0 this operation is an overwrite: no read
 of BF is required because the masked-out bits of the BF CR Field are
@@ -225,7 +223,7 @@ individual bits in BF may be set to 1 by ensuring that the required bit of
 
 **crweirder**
 
-    crweirder: BT, BFA, mask.mode
+    crweirder: BT,BFA,mask,mode
 
     creg = CR{BFA}
     n0 = mask[0] & (mode[0] == creg[0])
@@ -243,9 +241,9 @@ capability (BFT is 5 bits)
 
 **Example Pseudo-ops:**
 
-    mtcri BF, mode    mtcrweird BF, r0, 0, 0b1111.~mode
-    mtcrset BF, mask  mtcrweird BF, r0, 1, mask.0b0000
-    mtcrclr BF, mask  mtcrweird BF, r0, 1, mask.0b1111
+    mtcri BF, mode    mtcrweird BF, r0, 0, 0b1111,~mode
+    mtcrset BF, mask  mtcrweird BF, r0, 1, mask,0b0000
+    mtcrclr BF, mask  mtcrweird BF, r0, 1, mask,0b1111
 
 # Vectorised versions involving GPRs
 
@@ -255,7 +253,10 @@ to deriving the Vectorised versions of these instructions.
 Normally the progression of the SV for-loop would move on to the
 next register.  Instead however in the scalar case these instructions
 **remain in the same register** and insert or transfer between **bits**
-of the scalar integer source or destination.
+of the scalar integer source or destination.  The reason is that when
+using CR Fields as predicate masks and there is a need to transfer
+into a GPR, again for use as a predicate mask, the CR Field bits
+need to be efficiently packed into that one GPR (r3, r10 or r31).
 
 Further useful violation of the normal SV Elwidth override rules allows
 for packing (or unpacking) of multiple CR test results into (or out of)