Also as noted below, element-width override bits normally used
on the source is instead used to allow multiple results to be packed
-sequentially into the destination. *Destination elwidth overrides still apply*
-
-When the destination elwidth is default (0b00) the following packing occurs
-into destination elements:
-
-- SVRM bits 6:7 equal to 0b00 - one result element packed into one bit of each
- destination element (in the LSB)
-- SVRM bits 6:7 equal to 0b01 - two result elements packed into two bits of
- destination element (in the bottom two LSBs)
-- SVRM bits 6:7 equal to 0b10 - four result elements packed into four bits of
- destination element (in the bottom four LSBs)
-- SVRM bits 6:7 equal to 0b11 - eight result elements packed into four bits of
- destination element (in the bottom four LSBs)
-
-When for example the destination elwidth is 8-bit (0b11) then the destination
-element widths are 8-bit, and the result elements (grouped up to 8) still fit
-neatly into each 8-bit destination element.
+sequentially into the destination. *Destination elwidth overrides still apply*.
**mfcrrweird**
on the source is instead used to allow multiple results to be packed
into the destination. *Destination elwidth overrides still apply*
-Unlike `crrweird` however, the results are 4-bit wide, so the packing
-will begin to spill over to other destination elements. 8 results per
-destination at 4-bits each still fits into destination elwidth at 32-bit,
-but for 16-bit and 8-bit obviously this does not fit, and must split
-across to the next element
-
-When for example destination elwidth is 16-bit (0b10) the following packing
-occurs:
-
-- SVRM bits 6:7 equal to 0b00 - one 4-bit result element packed into the
- first 4-bits of the 16-bit destination element (in the first 4 LSBs)
-- SVRM bits 6:7 equal to 0b01 - two 4-bit result elements packed into the
- first 8-bits of the 16-bit destination element (in the first 8 LSBs)
-- SVRM bits 6:7 equal to 0b10 - four 4-bit result elements packed into each
- 16-bit destination element
-- SVRM bits 6:7 equal to 0b11 - eight 4-bit result elements, the first four
- of which are packed into the first 16-bit destination element, the
- second four of which are packed into the second 16-bit destination element.
-
**mtcrrweird**
mode is encoded in XO and is 4 bits
operand) elwidth field still sets the Integer element size as usual
(8/16/32/default)
- crrweird: RT, BB, mask.mode
+**crrweird: RT, BB, mask.mode**
for i in range(VL):
if BB.isvec:
of the INT Elements, the packing arrangement depending on both
elwidth override settings.
+**mfcrrweird: RT, BFA, mask.mode**
+
+Unlike `crrweird` the results are 4-bit wide, so the packing
+will begin to spill over to other destination elements. 8 results per
+destination at 4-bits each still fits into destination elwidth at 32-bit,
+but for 16-bit and 8-bit obviously this does not fit, and must split
+across to the next element
+
+When for example destination elwidth is 16-bit (0b10) the following packing
+occurs:
+
+- SVRM bits 6:7 equal to 0b00 - one 4-bit result element packed into the
+ first 4-bits of the 16-bit destination element (in the first 4 LSBs)
+- SVRM bits 6:7 equal to 0b01 - two 4-bit result elements packed into the
+ first 8-bits of the 16-bit destination element (in the first 8 LSBs)
+- SVRM bits 6:7 equal to 0b10 - four 4-bit result elements packed into each
+ 16-bit destination element
+- SVRM bits 6:7 equal to 0b11 - eight 4-bit result elements, the first four
+ of which are packed into the first 16-bit destination element, the
+ second four of which are packed into the second 16-bit destination element.
+
+Pseudocode example: note that dest elwidth overrides affect the
+packing of results. BB.elwidth in effect requests how many 4-bit
+result elements would like to be packed, but RT.elwidth determines
+the limit. Any parts of the destination elements not containing
+results are set to zero.
+
+ for i in range(VL):
+ if BB.isvec:
+ creg = CR{BB+i}
+ else:
+ creg = CR{BB}
+ n0 = mask[0] & (mode[0] == creg[0])
+ n1 = mask[1] & (mode[1] == creg[1])
+ n2 = mask[2] & (mode[2] == creg[2])
+ n3 = mask[3] & (mode[3] == creg[3])
+ result = n0||n1||n2||n3 # 4-bit result
+ if RT.isvec:
+ # RT.elwidth override can affect the packing
+ bwid = {0b00:64, 0b01:8, 0b10:16, 0b11:32}[RT.elwidth]
+ t4, t8 = min(4, bwid//2), min(8, bwid//2)
+ # yes, really, the CR's elwidth field determines
+ # the bit-packing into the INT!
+ if BB.elwidth == 0b00:
+ # pack 1 result into 64-bit registers
+ idx, boff = i, 0
+ if BB.elwidth == 0b01:
+ # pack 2 results sequentially into INT registers
+ idx, boff = i//2, i%2
+ if BB.elwidth == 0b10:
+ # pack 4 results sequentially into INT registers
+ idx, boff = i//t4, i%t4
+ if BB.elwidth == 0b11:
+ # pack 8 results sequentially into INT registers
+ idx, boff = i//t8, i%t8
+ else:
+ # exceeding VL=16 is UNDEFINED
+ idx, boff = 0, i
+ iregs[RT+idx][60-boff*4:63-boff*4] = result
+
+
+
# v3.1 setbc instructions
There are additional setb conditional instructions in v3.1 (p129)
projects / libreriscv.git / blobdiff