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[libreriscv.git] / openpower / sv / discussion.mdwn

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@@ -28,3 +28,15 @@ Section 8.3 Simple-V Instruction Encoding
 Section 8.4 Simple-V Execution Model
 
 Section 8.5 Simple-V Instruction Descriptions {setvl etc.}
+
+# questions
+
+There is much confusion about what the little-endian mapping of the register file means and how it is carried out. Do the registers effectively get byte-swapped by bits? by bytes? by elements? Isn't the LE mapping going to be extremely awkward in a system running in big-endian mode?
+Similarly, addressing the CR file by bit with little-endian numbering seems like it will create awkwardness.
+Does "truncate" mean the same as "terminate" here?
+Emulating 64-bit processors on a 32-bit CPU is not an objective. Perhaps your comments on the existing Power ISA could be toned down a bit?
+Phrases like "Cray-style vectors" and "DSP-style zero-overhead looping" are not particularly informative or well-defined, since many people in your audience will not be familiar either with Cray computer architecture or with DSPs.
+The process of taking interrupts, what state is saved and how, and then restored so execution can continue, all need to be spelled out in more detail. Can an asynchronous interrupt (e.g. external interrupt) occur in the middle of a vectorized instruction? How does that work?
+There seems to be no provision for saving SVSTATE when an event-based branch (Book II chapter 6) occurs. Should there be?
+How do vectorized conditional branches work and how is SVLR used?
+How do vectorized floating-point instructions set FPSCR, given that it isn't vectorized?