(no commit message)

[libreriscv.git] / openpower / sv / estimate-compression.py

diff --git a/openpower/sv/estimate-compression.py b/openpower/sv/estimate-compression.py
index 1d38b5feb9c7aab21e8028a2d44940d8e96a446f..94c0237fdfc14f79475137f1f2d0185be7f1afcf 100644 (file)
--- a/openpower/sv/estimate-compression.py
+++ b/openpower/sv/estimate-compression.py
@@ -101,7 +101,7 @@ def same01(opcode, ops):
         return 0
 
 # Registers representable in a made-up 3-bit mapping.
-cregs2 = { 1, 2, 3, 4, 5, 6, 7, 31 }
+cregs2 = { 9, 1, 2, 3, 31, 10, 30, 4 }
 
 # Return true iff mop is a regular register present in cregs2
 def bin2regs3(mop):