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[libreriscv.git] / openpower / sv / example_dep_matrices.mdwn

diff --git a/openpower/sv/example_dep_matrices.mdwn b/openpower/sv/example_dep_matrices.mdwn
index 3a33c42c95bc2ac4b050cab3e45d74bf912d38d2..142c95384564b492fd92c6fc36fdddc47e0ef141 100644 (file)
--- a/openpower/sv/example_dep_matrices.mdwn
+++ b/openpower/sv/example_dep_matrices.mdwn
@@ -19,3 +19,7 @@ See <https://bugs.libre-soc.org/show_bug.cgi?id=213#c83>
 |S\_LOGIC1  | y  | y  | y  | y  | y  | y  | y  | y  |  ->    | ?    | ?    | ?    | ?    | ?    | ?    | ?    | ?    | y   | y   | y   | y   |
 |S\_LOGIC2  | y  | y  | y  | y  | y  | y  | y  | y  |  ->    | ?    | ?    | ?    | ?    | ?    | ?    | ?    | ?    | y   | y   | y   | y   |
 
+Register allocation associated with this DM layout: Vectors may *only* be allocated to Vector FPs if RA%4 == RB%4
+== RT%4 and all reg numbers are over 32.  otherwise they are allocated
+to *scalar* FUs which has significantly less computational resources
+but far greater crossbar routing.  This allows 4R1W regfiles to be used where normally ultra-costly 12R10W would be required.