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[libreriscv.git] / openpower / sv / example_dep_matrices.mdwn

diff --git a/openpower/sv/example_dep_matrices.mdwn b/openpower/sv/example_dep_matrices.mdwn
index 0c4002d94e525027a3527e697f80f19882acc2f5..142c95384564b492fd92c6fc36fdddc47e0ef141 100644 (file)
--- a/openpower/sv/example_dep_matrices.mdwn
+++ b/openpower/sv/example_dep_matrices.mdwn
@@ -2,6 +2,8 @@
 
 # Scalar with Vector "Lanes"
 
+See <https://bugs.libre-soc.org/show_bug.cgi?id=213#c83>
+
 | FU-REGS -| r0 | r1 | r2 | r3 | r4 | r5 | r6 | r7 |  FU-FU | L0A0 | L1A0 | L2A0 | L3A0 | L0A1 | L1A2 | L2A1 | L3A1 | SA1 | SA2 | SL1 | SL2 |
 |----------|----|----|----|----|----|----|----|----|--------|------|------|----- |------|------|------|------|------|-----|-----|-----|-----|
 |V\_L0\_ALU0| y  |    |    |    |  y |    |    |    |  ->    | y    |      |      |      | y    |      |      |      | ?   | ?   | ?   | ?   |
@@ -17,3 +19,7 @@
 |S\_LOGIC1  | y  | y  | y  | y  | y  | y  | y  | y  |  ->    | ?    | ?    | ?    | ?    | ?    | ?    | ?    | ?    | y   | y   | y   | y   |
 |S\_LOGIC2  | y  | y  | y  | y  | y  | y  | y  | y  |  ->    | ?    | ?    | ?    | ?    | ?    | ?    | ?    | ?    | y   | y   | y   | y   |
 
+Register allocation associated with this DM layout: Vectors may *only* be allocated to Vector FPs if RA%4 == RB%4
+== RT%4 and all reg numbers are over 32.  otherwise they are allocated
+to *scalar* FUs which has significantly less computational resources
+but far greater crossbar routing.  This allows 4R1W regfiles to be used where normally ultra-costly 12R10W would be required.