-Simple-V is a Scalable Vector ISA Extension specifically tailored
-for the uniquely powerful capabilities of the Power ISA.
+**Simple-V** is a Scalable Vector ISA Extension **specifically tailored**
+for the uniquely powerful capabilities of the Power ISA. **SVP64**
+is the instruction set format.
+We invented Simple-V to be simple because we don't like complicated.
**Simple-V does not modify harm or corrupt the existing Power ISA** and
does not interfere with an existing system. It needs only a small
It is extremely important to think of Simple-V as a 2-Dimensional ISA:
instructions vertical and registers horizontal otherwise it will be
difficult to grasp and appreciate its RISC simplicity.
-
Like all Cray-Style Scalable Vector ISAs, Simple-V binaries remain
-ubiquitous: the ISA uniform. GPUs may implement massive-wide
-SIMD back-ends, focussing on
-number-crunching. Existing Multi-issue Superscalar implementations may
-insert Simple-V between decode and issue with minimal disruption.
-Single-issue in-order implementations are very straightforward. All
-implementations regardless of back-end capability may execute the exact
+ubiquitous, the ISA uniform. The Compliancy Levels offer a means
+to scale up in complexity to meet the target application requirements.
+
+* GPUs may implement massive-wide SIMD back-ends, focussing on
+ number-crunching.
+* Existing Multi-issue Superscalar implementations may
+ insert Simple-V between decode and issue with minimal disruption.
+* Single-issue in-order implementations are very straightforward.
+* Inter-core communication (OpenCAPI, other) may still be utilised
+ because SVP64 fundamentally remains and respects the Power ISA.
+
+All implementations regardless of back-end capability may execute the exact
same binaries *(this is known to be extremely important to the Power ISA
ecosystem)*.
+*If not done as carefully as SVP64, the addition of any other Scalable
+Vector Extension would require a significant number of opcodes, putting
+further pressure on Major Opcode space which was never designed with
+Scalable Vectors in mind. Contrast with RISC-V which was
+designed over a 7 year period with Cray-style Vectors right from the start.*
+
+Even with this amount of time spent, SVP64 exceeds the capability of RVV.
+RISC-V could have been significantly enhanced if Simple V had been applied
+to it: this possibility was investigated very early but the decision was
+made to go with Power ISA instead.
-Simple-V is **not RISC-V and is not RISC-V Vectors**. NEC SX Aurora,
-RVV and Simple-V are all based on Cray-style Vectors hence the similarity,
-the provision of a `setvl` instruction and why they are each called
-"Scalable" Vectors because it is the `setvl` instruction that
-presents the programmer with explicit control over Vector length.
+Therefore it is crucial to note that
+Simple-V is **not RISC-V and is not RISC-V Vectors**.
+[NEC SX Aurora](https://sxauroratsubasa.sakura.ne.jp/documents/guide/pdfs/Aurora_ISA_guide.pdf),
+[RVV](https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc),
+[Simple-V](https://ftp.libre-soc.org/simple_v_spec.pdf) and
+[MRISC32](https://github.com/mrisc32/mrisc32)
+are all based on
+[Cray-style Scalable Vectors](https://en.m.wikipedia.org/wiki/Cray-1)
+of 50 years ago, hence the similarity,
+the provision of a `setvl` instruction, and why they are each called
+"Scalable" Vectors, because it is the `setvl` instruction that
+presents the **programmer** with explicit control over Vector length.
-ARM NEON, AVX-512 and ARM SVE2 are all Predicated SIMD ISAs and
-**do not provide Scalability to the Programmer** (SVE2 is **Silicon**
+VSX and NEON are PackedSIMD, and
+AVX-512 and ARM SVE2 are Predicated SIMD ISAs.
+**None of them provide Scalability to the Programmer**. SVE2 is **Silicon**
Scalable, not **Programmer** Scalable: the distinction is profoundly
-important).
-For Predicated SIMD, Programmers must emulate scaling
+important (already
+[causing problems](https://bugs.libre-soc.org/show_bug.cgi?id=893#c15) ).
+For Predicated SIMD, Programmers must emulate Cray-style scaling
through explicit predicate masking, which increases instruction count in
hot-loops.
-We invented Simple-V to be simple because we don't like complicated.
-Links to Simulator, installation scripts, and Unit tests:
-
-* Unit tests and simulator for Power ISA v3.0 and SVP64
- <https://git.libre-soc.org/?p=openpower-isa.git;a=tree;f=src/openpower/decoder/isa;hb=HEAD>
-* several thousand more ISA unit tests
- <https://git.libre-soc.org/?p=openpower-isa.git;a=tree;f=src/openpower/test;hb=HEAD>
-* demo, showing 4.5x reduction in program size for MP3 decode, greatly
- simplifies assembler development
- <https://git.libre-soc.org/?p=openpower-isa.git;a=tree;f=media/audio/mp3;hb=HEAD>
-* binutils support for SVP64
- <https://git.libre-soc.org/?p=binutils-gdb.git;a=shortlog;h=refs/heads/svp64-ng>
-* Documentation <https://libre-soc.org/docs>
-* Installation scripts <https://git.libre-soc.org/?p=dev-env-setup.git;a=blob;f=hdl-dev-repos;hb=HEAD>
+| description, URL |
+|---------------------------------------------------------------------------------------------|
+| **Unit tests and simulator for Power ISA v3.0 and SVP64** |
+| <https://git.libre-soc.org/?p=openpower-isa.git;a=tree;f=src/openpower/decoder/isa;hb=HEAD> |
+| **pypowersim tutorial** |
+| <https://libre-soc.org/docs/pypowersim/> |
+| **several thousand more ISA unit tests** |
+| <https://git.libre-soc.org/?p=openpower-isa.git;a=tree;f=src/openpower/test;hb=HEAD> |
+| **demo, showing 4.5x reduction in program size for MP3 decode, greatly simplifies assembler development** |
+| <https://git.libre-soc.org/?p=openpower-isa.git;a=tree;f=media/audio/mp3;hb=HEAD> |
+| **binutils support for DRAFT SVP64 (now upstream)** |
+| <https://git.libre-soc.org/?p=binutils-gdb.git;a=shortlog;h=refs/heads/svp64-ng> |
projects / libreriscv.git / blobdiff