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[libreriscv.git] / openpower / sv / fcvt.mdwn

diff --git a/openpower/sv/fcvt.mdwn b/openpower/sv/fcvt.mdwn
index 328109c68034c4f93c62890b4092aae3fc855964..27de2900e082aa566225acbd7b7678366d0cd64b 100644 (file)
--- a/openpower/sv/fcvt.mdwn
+++ b/openpower/sv/fcvt.mdwn
@@ -1,3 +1,5 @@
+[[!tag standards]]
+
 # SV FP Conversion
 
 OpenPOWER Scalar ISA requires that FP32 numbers be distributed throughout the bits of the underlying FP64 register such that at any time an FP64 opcode nay be used, without performing any kind of conversion, directly on that FP32 value.  Likewise if precision is not important an FP32 opcode may be called on an FP64 value without conversion needed.
@@ -12,4 +14,5 @@ see <https://bugs.libre-soc.org/show_bug.cgi?id=564> for discussion.
 
 # Higher to lower fmv
 
-Here is the possibility of overflow of the result, as well as rounding.  
+Here is the possibility of overflow of the result, as well as rounding.  Effectively, this becomes what `frsp` currently does, whilst `frsp` itself has its meaning change from "convert source to single precision" to to "convert source to half of src precision followed by conversion to dest precision" where those two precisions may *or may not* be the same.
+