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[libreriscv.git] / openpower / sv / implementation.mdwn

diff --git a/openpower/sv/implementation.mdwn b/openpower/sv/implementation.mdwn
index 1d2c7409adb1eeb47b4781b0582a4c031d7732a3..56cddb49f374f217f28b23fc4d6e25afe0a4a5dc 100644 (file)
--- a/openpower/sv/implementation.mdwn
+++ b/openpower/sv/implementation.mdwn
@@ -13,6 +13,8 @@ Links:
   assembler translator
 * <https://bugs.libre-soc.org/show_bug.cgi?id=577> gcc/binutils/svp64
 * <https://bugs.libre-soc.org/show_bug.cgi?id=241> gem5 / ISACaller simulator
+  - <https://bugs.libre-soc.org/show_bug.cgi?id=581> gem5 upstreaming
+
 
 # Code to convert