(no commit message)

[libreriscv.git] / openpower / sv / implementation.mdwn

diff --git a/openpower/sv/implementation.mdwn b/openpower/sv/implementation.mdwn
index f55d5c58a0bdc14923cf5678202990b65383d174..8264127dff5f6860847ff6c81a227bfc486b71ad 100644 (file)
--- a/openpower/sv/implementation.mdwn
+++ b/openpower/sv/implementation.mdwn
@@ -183,7 +183,7 @@ unit tests:
 * Condition Registers.  see note below
 * FPR (if present)
 
-When Rc=1 is encountered in an SVP64 Context the destination is different (TODO) i.e. not CR0 or CR1.  Implicit Rc=1 Condition Registers are still Vectorised but do **not** have EXTRA2/3 spec adjustments.  The only part if the EXTRA2/3 spec that is observed and respected is whether the CR is Vectorised (isvec).
+When Rc=1 is encountered in an SVP64 Context the destination is different (TODO) i.e. not CR0 or CR1.  Implicit Rc=1 Condition Registers are still Vectorized but do **not** have EXTRA2/3 spec adjustments.  The only part if the EXTRA2/3 spec that is observed and respected is whether the CR is Vectorized (isvec).
 
 ## Increasing register file sizes
 
@@ -251,10 +251,10 @@ TODO
 * <https://libre-soc.org/openpower/sv/propagation/>
 * <https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=src/openpower/sv/svp64.py;hb=HEAD>
 
-## Vectorised Branches
+## Vectorized Branches
 
 TODO [[sv/branches]]
 
-## Vectorised LD/ST
+## Vectorized LD/ST
 
 TODO [[sv/ldst]]