(no commit message)

[libreriscv.git] / openpower / sv / implementation.mdwn

diff --git a/openpower/sv/implementation.mdwn b/openpower/sv/implementation.mdwn
index 7860c9089fe1063781c5fe8b6700e5f361def18a..c2018946d89406a0ebcf7b56bb77154699a7600a 100644 (file)
--- a/openpower/sv/implementation.mdwn
+++ b/openpower/sv/implementation.mdwn
@@ -2,7 +2,7 @@
 
 This page covers and coordinates implementing SV.  The basic concept is
 to go step-by-step through the [[sv/overview]] adding each feature,
-one at a time.
+one at a time.  Caveats and notes are included so that other implementors may avoid some common pitfalls.
 
 Links:
 
@@ -48,6 +48,7 @@ These are prerequisite tasks:
 * PowerDecoder2 - both TestIssuer and ISACaller are dependent on this
   - <https://bugs.libre-soc.org/show_bug.cgi?id=588> underway
   - INT and CR EXTRA svp64 fields completed.
+* SVP64PowerDecoder2, used to identify SVP64 Prefixes.  DONE.
 
 People coordinating different tasks. This doesn't mean exclusive work on these areas it just means they are the "coordinator" and lead:
 
@@ -69,9 +70,9 @@ order: listed in [[sv/overview]]
 
 An autogenerator containing CSV files is available so that the task of creating decoders is not burdensome.  sv_analyse.py creates the CSV files, SVP64RM class picks them up.
 
-* ISACaller: TODO
+* ISACaller: part done.  svp64 detected, PowerDecoder2 in use
 * power-gem5: TODO
-* TestIssuer: TODO
+* TestIssuer: part done.  svp64 detected, PowerDecoder2 in use.
 * Microwatt: TODO
 * python-based assembler-translator: 40% done (lkcl)
 * c++ macros: underway (jacob)
@@ -91,7 +92,9 @@ Chosen values, fitting with v3.1B p12 "Sandbox" guidelines:
     704,SVSTATE,no,no,32
     720,SVSRR0,yes,yes,32
 
-* ISACaller: TODO
+Progress:
+
+* ISACaller: done
 * power-gem5: TODO
 * TestIssuer: TODO
 * Microwatt: TODO
@@ -127,15 +130,27 @@ This **includes** any exceptions, hence why SVSTATE exists and why SVSRR0 must b
 
 Due to the need for exceptions to occur in the middle, the loop should *not* be implemented as an actual for-loop, whilst recognising that optimised implementations may do multi-issue element execution as long as Program Order is preserved, just as it would be for the PC.
 
-* ISACaller: TODO
+* ISACaller: DONE, first revision <https://git.libre-soc.org/?p=soc.git;a=commitdiff;h=9078b2935beb4ba89dcd2af91bb5e3a0bcffbe71>
 * power-gem5: TODO
-* TestIssuer: TODO
+* TestIssuer: part done <https://git.libre-soc.org/?p=soc.git;a=commitdiff;h=92ba64ea13794dea71816be746a056d52e245651>
 * Microwatt: TODO
 
+Remember the following register files need to have for-loops, plus
+unit tests:
+
+* GPR
+* SPRs (yes, really: mtspr and mfspr are SV Context-extensible)
+* Condition Registers.  see note below
+* FPR (if present)
+
+When Rc=1 is encountered in an SVP64 Context the destination is different (TODO) i.e. not CR0 or CR1.  Implicit Rc=1 Condition Registers are still Vectorised but do **not** have EXTRA2/3 spec adjustments.  The only part if the EXTRA2/3 spec that is observed and respected is whether the CR is Vectorised (isvec).
+
 ## Increasing register file sizes
 
 TODO.  INTs, FPs, CRs, these all increase to 128.  Welcome To Vector ISAs.
 
+At the same time the `Rc=1` CR offsets normslly CR0 and CR1 for fixed and FP scalar may also be adjusted.
+
 ## Single Predication
 
 TODO