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[libreriscv.git] / openpower / sv / implementation.mdwn

diff --git a/openpower/sv/implementation.mdwn b/openpower/sv/implementation.mdwn
index 71e9925ba606d04aeed8197921c2a5219ed6a2d2..eea188067b26332748a1041a08d3bd6d248d9be5 100644 (file)
--- a/openpower/sv/implementation.mdwn
+++ b/openpower/sv/implementation.mdwn
@@ -2,7 +2,7 @@
 
 This page covers and coordinates implementing SV.  The basic concept is
 to go step-by-step through the [[sv/overview]] adding each feature,
-one at a time.
+one at a time.  Caveats and notes are included so that other implementors may avoid some common pitfalls.
 
 Links:
 
@@ -120,6 +120,15 @@ SV's SVSTATE context is effectively a Sub-PC.  On exceptions the PC is saved int
 * TestIssuer: TODO
 * Microwatt: TODO
 
+## Illegal instruction exceptions
+
+Anything not listed as SVP64 extended must raise an illegal exception if prefixed. setvl, branch, mtmsr, mfmsr at the minimum.
+
+* ISACaller: TODO
+* power-gem5: TODO
+* TestIssuer: TODO
+* Microwatt: TODO
+
 ## VL for-loop
 
 main SV for-loop, as a FSM, updating `SVSTATE.srcstep`, using it as the index in the for-loop from 0 to VL-1.  Register numbers are incremented by one if marked as vector.
@@ -140,13 +149,17 @@ unit tests:
 
 * GPR
 * SPRs (yes, really: mtspr and mfspr are SV Context-extensible)
-* Condition Registers
+* Condition Registers.  see note below
 * FPR (if present)
 
+When Rc=1 is encountered in an SVP64 Context the destination is different (TODO) i.e. not CR0 or CR1.  Implicit Rc=1 Condition Registers are still Vectorised but do **not** have EXTRA2/3 spec adjustments.  The only part if the EXTRA2/3 spec that is observed and respected is whether the CR is Vectorised (isvec).
+
 ## Increasing register file sizes
 
 TODO.  INTs, FPs, CRs, these all increase to 128.  Welcome To Vector ISAs.
 
+At the same time the `Rc=1` CR offsets normslly CR0 and CR1 for fixed and FP scalar may also be adjusted.
+
 ## Single Predication
 
 TODO