(no commit message)

[libreriscv.git] / openpower / sv / implementation.mdwn

diff --git a/openpower/sv/implementation.mdwn b/openpower/sv/implementation.mdwn
index c26a646b7a005596dccc90087f1a12ce7b21cf72..f55d5c58a0bdc14923cf5678202990b65383d174 100644 (file)
--- a/openpower/sv/implementation.mdwn
+++ b/openpower/sv/implementation.mdwn
@@ -24,6 +24,7 @@ Links:
 * <https://bugs.libre-soc.org/show_bug.cgi?id=618> ISACaller add single/twin Predication
 * <https://bugs.libre-soc.org/show_bug.cgi?id=619> tracking manual augmentation of CSV files
 * <https://bugs.libre-soc.org/show_bug.cgi?id=636> add zeroing and exceptions
+* <https://bugs.libre-soc.org/show_bug.cgi?id=663> element-width overrides
 
 # Code to convert
 
@@ -97,7 +98,7 @@ Links:
 
 This is a peer of MSR but is stored in an SPR.  It should be considered part of the state of PC+MSR because SVSTATE is effectively a Sub-PC.
 
-Chosen values, fitting with v3.1B p12 "Sandbox" guidelines:
+Chosen values, fitting with v3.1 / v3.0C p12 "Sandbox" guidelines:
 
     num name    priv  width
     704,SVSTATE,no,no,32
@@ -141,11 +142,13 @@ Links:
 
 SV's SVSTATE context is effectively a Sub-PC.  On exceptions the PC is saved into SRR0: it should come as no surprise that SVSTATE must be treated exactly the same.  SVSRR0 therefore is added to the list to be saved/restored in **exactly** the same way and time as SRR0 and SRR1.  This is fundamental and absolutely critical to view SVSTATE as a full peer of PC (CIA, NIA).
 
-* ISACaller: TODO
+* ISACaller: TODO unit test
 * power-gem5: TODO
 * TestIssuer: TODO
 * Microwatt: TODO
 
+* added ISACaller SVSRR0 save <https://git.libre-soc.org/?p=openpower-isa.git;a=commitdiff;h=25071d491dba94495657796eb6ff10eb6499257f>
+
 ## Illegal instruction exceptions
 
 Anything not listed as SVP64 extended must raise an illegal exception if prefixed. setvl, branch, mtmsr, mfmsr at the minimum.
@@ -208,6 +211,13 @@ src and dest predicate mask is "All 1s".
 Bear in mind that srcstep+deststep are a form of back-to-back
 VGATHER+VSCATTER
 
+Watch out in zeroing! CR0 will *not* be set (itself) to zero:
+the CR0.eq flag will be set because the *result* is still tested.
+correction: CR0-and-any-other-Vector-of-CR-fields (Vector elements
+have their corresponding CR field, so the test of zero needs to
+be done for the associated *element* result, not jam absolutely
+every element vector test *into* CR0)
+
 Progress:
 
 * TestIssuer <https://bugs.libre-soc.org/show_bug.cgi?id=617> 
@@ -218,4 +228,33 @@ Progress:
 
 ## Element width overrides
 
+<https://bugs.libre-soc.org/show_bug.cgi?id=663>
+
+* Pseudocode: TODO
+* Simulator: TODO
+* TestIssuer: TODO
+* unit tests: TODO
+* power-gem5: TODO
+* cavatools: TODO
+
+## Reduce Mode
+
 TODO
+
+## Saturation Mode
+
+TODO
+
+## REMAP and Context Propagation
+
+* <https://libre-soc.org/openpower/sv/remap/>
+* <https://libre-soc.org/openpower/sv/propagation/>
+* <https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=src/openpower/sv/svp64.py;hb=HEAD>
+
+## Vectorised Branches
+
+TODO [[sv/branches]]
+
+## Vectorised LD/ST
+
+TODO [[sv/ldst]]