(no commit message)

[libreriscv.git] / openpower / sv / implementation.mdwn

diff --git a/openpower/sv/implementation.mdwn b/openpower/sv/implementation.mdwn
index b5ecc5034a4b0b35828a252532fbf9080571e21f..f55d5c58a0bdc14923cf5678202990b65383d174 100644 (file)
--- a/openpower/sv/implementation.mdwn
+++ b/openpower/sv/implementation.mdwn
@@ -24,6 +24,7 @@ Links:
 * <https://bugs.libre-soc.org/show_bug.cgi?id=618> ISACaller add single/twin Predication
 * <https://bugs.libre-soc.org/show_bug.cgi?id=619> tracking manual augmentation of CSV files
 * <https://bugs.libre-soc.org/show_bug.cgi?id=636> add zeroing and exceptions
+* <https://bugs.libre-soc.org/show_bug.cgi?id=663> element-width overrides
 
 # Code to convert
 
@@ -97,7 +98,7 @@ Links:
 
 This is a peer of MSR but is stored in an SPR.  It should be considered part of the state of PC+MSR because SVSTATE is effectively a Sub-PC.
 
-Chosen values, fitting with v3.1B p12 "Sandbox" guidelines:
+Chosen values, fitting with v3.1 / v3.0C p12 "Sandbox" guidelines:
 
     num name    priv  width
     704,SVSTATE,no,no,32
@@ -227,7 +228,14 @@ Progress:
 
 ## Element width overrides
 
-TODO
+<https://bugs.libre-soc.org/show_bug.cgi?id=663>
+
+* Pseudocode: TODO
+* Simulator: TODO
+* TestIssuer: TODO
+* unit tests: TODO
+* power-gem5: TODO
+* cavatools: TODO
 
 ## Reduce Mode
 
@@ -236,3 +244,17 @@ TODO
 ## Saturation Mode
 
 TODO
+
+## REMAP and Context Propagation
+
+* <https://libre-soc.org/openpower/sv/remap/>
+* <https://libre-soc.org/openpower/sv/propagation/>
+* <https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=src/openpower/sv/svp64.py;hb=HEAD>
+
+## Vectorised Branches
+
+TODO [[sv/branches]]
+
+## Vectorised LD/ST
+
+TODO [[sv/ldst]]