* <https://bugs.libre-soc.org/show_bug.cgi?id=588> PowerDecoder2
* <https://bugs.libre-soc.org/show_bug.cgi?id=587> setvl ancillary tasks
(instruction form SVL-Form, field designations, pseudocode, SPR allocation)
+* <https://bugs.libre-soc.org/show_bug.cgi?id=615> agree sv assembly syntax
+* <https://bugs.libre-soc.org/show_bug.cgi?id=617> TestIssuer add single/twin Predication
+* <https://bugs.libre-soc.org/show_bug.cgi?id=618> ISACaller add single/twin Predication
+* <https://bugs.libre-soc.org/show_bug.cgi?id=619> tracking manual augmentation of CSV files
+* <https://bugs.libre-soc.org/show_bug.cgi?id=636> add zeroing and exceptions
+* <https://bugs.libre-soc.org/show_bug.cgi?id=663> element-width overrides
# Code to convert
-There are four projects:
+There are five projects:
* TestIssuer (the HDL)
* ISACaller (the python-based simulator)
* power-gem5 (a cycle accurate simulator)
* Microwatt (VHDL)
+* gcc and binutils
Each of these needs to have SV augmentation, and the best way to
do it is if they are all done at the same time, implementing the same
* Cole:
* Luke: ISACaller, python-assembler-generator-class
* Tobias:
-* Alexandre: binutils-svp64-assembler
+* Alexandre: binutils-svp64-assembler and gcc
* Paul: microwatt
# Adding SV
* python-based assembler-translator: 40% done (lkcl)
* c++ macros: underway (jacob)
-Note when decoding the RM intobits different modes that LDST interprets the 5 mode bits differently not just on whether it is LD/ST bit also what *type* of LD/ST. Immediate LD/ST is further qualified to indicate if it operates in element-strided or unit-strided mode. However Indexed LD/ST is not.
+Note when decoding the RM into bits different modes that LDST interprets the 5 mode bits differently not just on whether it is LD/ST bit also what *type* of LD/ST. Immediate LD/ST is further qualified to indicate if it operates in element-strided or unit-strided mode. However Indexed LD/ST is not.
+
+**IMPORTANT**! when spotting RA=0 in some instructions it is critical to note that the *full **seven** bits* are used (those from EXTRA2/3 included) because RA is no longer only five bits.
Links:
This is a peer of MSR but is stored in an SPR. It should be considered part of the state of PC+MSR because SVSTATE is effectively a Sub-PC.
-Chosen values, fitting with v3.1B p12 "Sandbox" guidelines:
+Chosen values, fitting with v3.1 / v3.0C p12 "Sandbox" guidelines:
num name priv width
704,SVSTATE,no,no,32
* LibreSOC DMI/JTAG: TODO
* Microwatt DMI: TODO
* power-gem5 remote gdb: TODO
-* TestIssuer: TODO
+* TestIssuer: DONE (read-only at least) <https://git.libre-soc.org/?p=soc.git;a=commitdiff;h=4d5482810c980ff927ccec62968a40a490ea86eb>
Links:
SV's SVSTATE context is effectively a Sub-PC. On exceptions the PC is saved into SRR0: it should come as no surprise that SVSTATE must be treated exactly the same. SVSRR0 therefore is added to the list to be saved/restored in **exactly** the same way and time as SRR0 and SRR1. This is fundamental and absolutely critical to view SVSTATE as a full peer of PC (CIA, NIA).
-* ISACaller: TODO
+* ISACaller: TODO unit test
* power-gem5: TODO
* TestIssuer: TODO
* Microwatt: TODO
+* added ISACaller SVSRR0 save <https://git.libre-soc.org/?p=openpower-isa.git;a=commitdiff;h=25071d491dba94495657796eb6ff10eb6499257f>
+
## Illegal instruction exceptions
Anything not listed as SVP64 extended must raise an illegal exception if prefixed. setvl, branch, mtmsr, mfmsr at the minimum.
* ISACaller: DONE, first revision <https://git.libre-soc.org/?p=soc.git;a=commitdiff;h=9078b2935beb4ba89dcd2af91bb5e3a0bcffbe71>
* power-gem5: TODO
-* TestIssuer: part done <https://git.libre-soc.org/?p=soc.git;a=commitdiff;h=92ba64ea13794dea71816be746a056d52e245651>
+* TestIssuer:
+ - part done <https://git.libre-soc.org/?p=soc.git;a=commitdiff;h=92ba64ea13794dea71816be746a056d52e245651>
+ - done <https://git.libre-soc.org/?p=soc.git;a=commitdiff;h=97136d71397f420479d601dcb80f0df4abf73d22>
* Microwatt: TODO
Remember the following register files need to have for-loops, plus
At the same time the `Rc=1` CR offsets normslly CR0 and CR1 for fixed and FP scalar may also be adjusted.
-## Single Predication
+## Single and Twin Predication
-TODO
+both CR and INT predication is needed, as well as zeroing in both.
+the order is best done as follows:
+
+* INT-based single
+* CR-based single
+* srcstep+dststep
+* INT-based twin
+* CR-based twin
+* Zeroing single
+* Zeroing twin
+
+Best done as a FSM that "advances" srcstep and dststep over the
+zeros in their respective predicate masks, *including* when the
+src and dest predicate mask is "All 1s".
+
+Bear in mind that srcstep+deststep are a form of back-to-back
+VGATHER+VSCATTER
+
+Watch out in zeroing! CR0 will *not* be set (itself) to zero:
+the CR0.eq flag will be set because the *result* is still tested.
+correction: CR0-and-any-other-Vector-of-CR-fields (Vector elements
+have their corresponding CR field, so the test of zero needs to
+be done for the associated *element* result, not jam absolutely
+every element vector test *into* CR0)
+
+Progress:
+
+* TestIssuer <https://bugs.libre-soc.org/show_bug.cgi?id=617>
+ and Zeroing <https://bugs.libre-soc.org/show_bug.cgi?id=636>
+* ISACaller <https://bugs.libre-soc.org/show_bug.cgi?id=618>
+* power-gem5: TODO
+* Microwatt: TODO
## Element width overrides
+<https://bugs.libre-soc.org/show_bug.cgi?id=663>
+
+* Pseudocode: TODO
+* Simulator: TODO
+* TestIssuer: TODO
+* unit tests: TODO
+* power-gem5: TODO
+* cavatools: TODO
+
+## Reduce Mode
+
+TODO
+
+## Saturation Mode
+
TODO
+
+## REMAP and Context Propagation
+
+* <https://libre-soc.org/openpower/sv/remap/>
+* <https://libre-soc.org/openpower/sv/propagation/>
+* <https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=src/openpower/sv/svp64.py;hb=HEAD>
+
+## Vectorised Branches
+
+TODO [[sv/branches]]
+
+## Vectorised LD/ST
+
+TODO [[sv/ldst]]
projects / libreriscv.git / blobdiff