* <https://bugs.libre-soc.org/show_bug.cgi?id=618> ISACaller add single/twin Predication
* <https://bugs.libre-soc.org/show_bug.cgi?id=619> tracking manual augmentation of CSV files
* <https://bugs.libre-soc.org/show_bug.cgi?id=636> add zeroing and exceptions
+* <https://bugs.libre-soc.org/show_bug.cgi?id=663> element-width overrides
# Code to convert
This is a peer of MSR but is stored in an SPR. It should be considered part of the state of PC+MSR because SVSTATE is effectively a Sub-PC.
-Chosen values, fitting with v3.1B p12 "Sandbox" guidelines:
+Chosen values, fitting with v3.1 / v3.0C p12 "Sandbox" guidelines:
num name priv width
704,SVSTATE,no,no,32
## Element width overrides
+<https://bugs.libre-soc.org/show_bug.cgi?id=663>
+
+* Pseudocode: TODO
+* Simulator: TODO
+* TestIssuer: TODO
+* unit tests: TODO
+* power-gem5: TODO
+* cavatools: TODO
+
+## Reduce Mode
+
+TODO
+
+## Saturation Mode
+
TODO
+
+## REMAP and Context Propagation
+
+* <https://libre-soc.org/openpower/sv/remap/>
+* <https://libre-soc.org/openpower/sv/propagation/>
+* <https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=src/openpower/sv/svp64.py;hb=HEAD>
+
+## Vectorised Branches
+
+TODO [[sv/branches]]
+
+## Vectorised LD/ST
+
+TODO [[sv/ldst]]