and with its focus on modern 3D GPU hybrid workloads represents an
important new potential use-case for OpenPOWER.
-The progressive development of the Scalar parts of the Power ISA assumed
-that VSX would be there to complement it. However With VMX/VSX
+Prior to the formation of the Compliancy Levels first introduced
+in v3.0C and v3.1
+the progressive historic development of the Scalar parts of the Power ISA assumed
+that VSX would always be there to complement it. However With VMX/VSX
**not available** in the newly-introduced SFFS Compliancy Level, the
existing non-VSX conversion/data-movement instructions require load/store
instructions (slow and expensive) to transfer data between the FPRs and
For the sake of simplicity, the FP -> Integer conversion semantics generalized from those used by JavaScripts's `ToInt32` abstract operation will be referred to as [JavaScript conversion semantics](#fp-to-int-javascript-conversion-semantics).
+This instruction is present in ARM assembler as FJCVTZS
+<https://developer.arm.com/documentation/dui0801/g/hko1477562192868>
+
### Other languages
TODO: review and investigate other language semantics
Integer operands and results being in the GPR is the key differentiator between the proposed instructions
(the entire rationale) compated to existing Scalar Power ISA.
-All existing Power ISA Scalar conversion instructions, all
+In all existing Power ISA Scalar conversion instructions, all
operands are FPRs, even if the format of the source or destination
data is actually a scalar integer.
Note that source and destination widths can be overridden by SimpleV
SVP64, and that SVP64 also has Saturation Modes *in addition*
to those independently described here. SVP64 Overrides and Saturation
-work on *both* Fixed *and* Floating Point.
+work on *both* Fixed *and* Floating Point operands and results.
The interactions with SVP64
are explained in the [[int_fp_mv/appendix]]