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[libreriscv.git] / openpower / sv / int_fp_mv.mdwn

diff --git a/openpower/sv/int_fp_mv.mdwn b/openpower/sv/int_fp_mv.mdwn
index 1f4dc044afb2b0541c89c4e3b3cf18d4ac9b2410..ad1740f0fb9078984e909a3b30b659dd1e63ee5d 100644 (file)
--- a/openpower/sv/int_fp_mv.mdwn
+++ b/openpower/sv/int_fp_mv.mdwn
@@ -45,9 +45,11 @@ in v3.0C and v3.1
 the progressive historic development of the Scalar parts of the Power ISA assumed
 that VSX would always be there to complement it. However With VMX/VSX 
 **not available** in the newly-introduced SFFS Compliancy Level, the
-existing non-VSX conversion/data-movement instructions require load/store
+existing non-VSX conversion/data-movement instructions require 
+a Vector of load/store
 instructions (slow and expensive) to transfer data between the FPRs and
-the GPRs.  For a 3D GPU this kills any modern competitive edge.
+the GPRs.  For a modern 3D GPU this kills any possibility of a
+competitive edge.
 Also, because SimpleV needs efficient scalar instructions in
 order to generate efficient vector instructions, adding new instructions
 for data-transfer/conversion between FPRs and GPRs multiplies the savings.
@@ -108,21 +110,22 @@ These are like a variant of `fmvfg` and `oris`, combined.
 Power ISA currently requires a large
 number of instructions to get Floating Point constants into registers.
 `fmvis` on its own is equivalent to BF16 to FP32/64 conversion,
-but if followed up by `fishmv` an additional 16 bits of accuracy in the
+but if followed up by `frlsi` an additional 16 bits of accuracy in the
 mantissa may be achieved.
 
 *IBM may consider it worthwhile to extend these two instructions to
-v3.1 Prefixed (`pfmvis` and `pfishmv`). If so it is recommended that
-`pfmvis` load a full FP32 immediate and `pfishmv` extend the lower
-32-bits to construct a full FP64 immediate.*
+v3.1 Prefixed (`pfmvis` and `pfrlsi`). If so it is recommended that
+`pfmvis` load a full FP32 immediate and `pfrlsi` supplies the three high
+missing exponent bits (numbered 8 to 10) and the lower additional
+29 mantissa bits (23 to 51) needed to construct a full FP64 immediate.*
 
 ## Load BF16 Immediate
 
-`fmvis FRS, FI`
+`fmvis FRS, D`
 
-Reinterprets `FI << 16` as a 32-bit float, which is then converted to a
+Reinterprets `D << 16` as a 32-bit float, which is then converted to a
 64-bit float and written to `FRS`.  This is equivalent to reinterpreting
-`FI` as a `BF16` and converting to 64-bit float.
+`D` as a `BF16` and converting to 64-bit float.
 There is no need for an Rc=1 variant because this is an immediate loading
 instruction.
 
@@ -163,9 +166,9 @@ Pseudocode:
     fp32 = bf16 || [0]*16
     FRS = Single_to_Double(fp32)
 
-## Float Immediate, Second Half <a name="fishmv"></a>
+## Float Replace Lower-Half Single, Immediate <a name="frlsi"></a>
 
-`fishmv FRS, FI`
+`frlsi FRS, D`
 
 DX-Form:
 
@@ -176,14 +179,16 @@ DX-Form:
 Strategically similar to how `oris` is used to construct
 32-bit Integers, an additional 16-bits of immediate is
 inserted into `FRS` to extend its accuracy to
-a full FP32. If a prior `fmvis` instruction had been used to
-set the upper 16-bits of an FP32 value, `fishmv` contains the
+a full FP32 (stored as usual in FP64 Format within the FPR).
+If a prior `fmvis` instruction had been used to
+set the upper 16-bits of an FP32 value, `frlsi` contains the
 lower 16-bits.
 
-The key difference between using `li` and `oris` to construxt 32-bit
-GPR Immediates and `fishmv` is that the `fmvis` will have converted
-the `BF16` to FP64 (Double) format. This is taken into consideration
-as can be seen in the pseudocode below
+The key difference between using `li` and `oris` to construct 32-bit
+GPR Immediates and `frlsi` is that the `fmvis` will have converted
+the `BF16` immediate to FP64 (Double) format.
+This is taken into consideration
+as can be seen in the pseudocode below.
 
 Pseudocode:
 
@@ -203,7 +208,7 @@ Example:
 # first the upper bits, happens to be +1.0
 fmvis f4, 0x3F80 # writes +1.0 to f4
 # now write the lower 16 bits of an FP32
-fishmv f4, 0x8000 # writes +1.00390625 to f4
+frlsi f4, 0x8000 # writes +1.00390625 to f4
 ```
 
 # Moves
@@ -395,16 +400,16 @@ are all set as normal for any GPR instructions that overflow.
 
 * `fcvttgw RT, FRA, Mode`
   Convert from 64-bit float to 32-bit signed integer, writing the result
-  to the GPR `RT`. Converts using [mode `Mode`]
+  to the GPR `RT`. Converts using [mode `Mode`]. Similar to `fctiw` or `fctiwz`
 * `fcvttguw RT, FRA, Mode`
   Convert from 64-bit float to 32-bit unsigned integer, writing the result
-  to the GPR `RT`. Converts using [mode `Mode`]
+  to the GPR `RT`. Converts using [mode `Mode`]. Similar to `fctiwu` or `fctiwuz`
 * `fcvttgd RT, FRA, Mode`
   Convert from 64-bit float to 64-bit signed integer, writing the result
-  to the GPR `RT`. Converts using [mode `Mode`]
+  to the GPR `RT`. Converts using [mode `Mode`]. Similar to `fctid` or `fctidz`
 * `fcvttgud RT, FRA, Mode`
   Convert from 64-bit float to 64-bit unsigned integer, writing the result
-  to the GPR `RT`. Converts using [mode `Mode`]
+  to the GPR `RT`. Converts using [mode `Mode`]. Similar to `fctidu` or `fctiduz`
 * `fcvtstgw RT, FRA, Mode`
   Convert from 32-bit float to 32-bit signed integer, writing the result
   to the GPR `RT`. Converts using [mode `Mode`]