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[libreriscv.git] / openpower / sv / ldst.mdwn

diff --git a/openpower/sv/ldst.mdwn b/openpower/sv/ldst.mdwn
index 9246e70822a218c4d5f9f3cb38275cfe3a1ccb9d..8fe06719dedd990033c54e22a62ca40a7129ca65 100644 (file)
--- a/openpower/sv/ldst.mdwn
+++ b/openpower/sv/ldst.mdwn
@@ -184,11 +184,11 @@ The table for [[sv/svp64]] for `immed(RA)` is:
 
 | 0-1 |  2  |  3   4  |  description               |
 | --- | --- |---------|--------------------------- |
-| 00  | 0   |  dz els | normal mode                |
-| 00  | 1   |  dz shf | shift mode                 |
+| 00  | 0   |  zz els | normal mode                |
+| 00  | 1   |  zz shf | shift mode                 |
 | 01  | inv | CR-bit  | Rc=1: ffirst CR sel        |
 | 01  | inv | els RC1 |  Rc=0: ffirst z/nonz       |
-| 10  |   N | dz  els |  sat mode: N=0/1 u/s       |
+| 10  |   N | zz  els |  sat mode: N=0/1 u/s       |
 | 11  | inv | CR-bit  |  Rc=1: pred-result CR sel  |
 | 11  | inv | els RC1 |  Rc=0: pred-result z/nonz  |
 
@@ -236,7 +236,7 @@ The modes for `RA+RB` indexed version are slightly different:
 | 01  | SEA | dz sz  | Strided (scalar only source)   |
 | 10  |   N | dz   sz |  sat mode: N=0/1 u/s |
 | 11  | inv | CR-bit  |  Rc=1: pred-result CR sel |
-| 11  | inv | dz  RC1 |  Rc=0: pred-result z/nonz |
+| 11  | inv | zz  RC1 |  Rc=0: pred-result z/nonz |
 
 Vector Indexed Strided Mode is qualified as follows:
 
@@ -293,7 +293,9 @@ LD/ST Fail-First. It is however critically important to remember that
 the first element LD/ST **MUST** be treated as an ordinary LD/ST, i.e.
 **MUST** raise exceptions exactly like an ordinary LD/ST.
 
-For ffirst LD/STs, VL may be truncated arbitrarily to a nonzero value for any implementation-specific reason. For example: it is perfectly reasonable for implementations to alter VL when ffirst LD or ST operations are initiated on a nonaligned boundary, such that within a loop the subsequent iteration of that loop begins subsequent ffirst LD/ST operations on an aligned boundary. Likewise, to reduce workloads or balance resources.
+For ffirst LD/STs, VL may be truncated arbitrarily to a nonzero value for any implementation-specific reason. For example: it is perfectly reasonable for implementations to alter VL when ffirst LD or ST operations are initiated on a nonaligned boundary, such that within a loop the subsequent iteration of that loop begins subsequent ffirst LD/ST operations on an aligned boundary
+such as the beginning of a cache line, or beginning of a Virtual Memory
+page. Likewise, to reduce workloads or balance resources.
 
 Vertical-First Mode is slightly strange in that only one element
 at a time is ever executed anyway.  Given that programmers may