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[libreriscv.git] / openpower / sv / major_opcode_allocation.mdwn

diff --git a/openpower/sv/major_opcode_allocation.mdwn b/openpower/sv/major_opcode_allocation.mdwn
index 054bb5bb7021bd0f516e3c6501da2e99cb78ddce..f94733e8391450430f4ca77417ae255706fa8c30 100644 (file)
--- a/openpower/sv/major_opcode_allocation.mdwn
+++ b/openpower/sv/major_opcode_allocation.mdwn
@@ -26,7 +26,7 @@ likewise switch into the same.
 VBLOCK can be added later by using further VSX dedicated major opcodes
 (EXT62, EXT60)
 
-* EXT00 - unused
+* EXT00 - unused (one instruction: attn)
 * EXT01 - v3.1B prefix
 * EXT02 - twi
 * EXT03 - tdi
@@ -35,7 +35,10 @@ VBLOCK can be added later by using further VSX dedicated major opcodes
 * EXT06 - vector
 * EXT07 - mulli
 * EXT09 - reserved
+* EXT17 - unused (2 instructions: sc, scv)
 * EXT22 - reserved sandbox
+* EXT46 - lmw
+* EXT47 - stmw
 * EXT56 - lq
 * EXT57 - vector ld
 * EXT58 - ld (leave ok)
@@ -47,12 +50,58 @@ VBLOCK can be added later by using further VSX dedicated major opcodes
 
 Potential allocations:
 
-* EXT00/01 - Compressed 16 bit
-* EXT02/03 - SV-P48 / SV-C32
-* EXT04/05 - SV-P64 / SV-C48
-* EXT06/07 - SV-C64 / ?
-* EXT56/57 - SV-C32-Swizzle
-* EXT60/62 - VBLOCK
+    |  hword 0   | hword1  |  hword2    |  hword 3   |
+    EXT00/01 - C 10bit -> 16bit
+    EXT60/62 - VBLOCK
+    EXT09/17 - SV-C32 and other SV-C
+    EXT06/07 - SV-C32-Swizzle and other SV-C-Swizzle
+    EXT02/03 - SV-P48                
+    EXT04/05 - SV-P64
+    EXT56/57 - Predicated-SV-P48
+    EXT46/47 - Predicated SV-P64
+
+Spare:
+
+* EXT22
+
+## C10/16 FSM
+
+    if EXT == 00/01
+         start @ 10bit
+    if state==10bit:
+         if bit15:
+             next = 16bit
+         else:
+             next = Standard
+    if state==16bit:
+         if bit0 & bit15:
+             insn = C.immediate
+         if ~bit15:
+             if ~bit0:
+                 next = Standard
+             else
+                 next = Standard.then.16bit
+
+## SV-Compressed FSM
+
+    if EXT == 09/17:
+        if bit0:
+             SV.mode = 
+
+# Major opcode map
+
+Table 9: Primary Opcode Map (opcode bits 0:5)
+
+        |  000   |   001 |  010  | 011   |  100  |    101 |  110  |  111
+    000 |        |       |  tdi  | twi   | EXT04 |        |       | mulli | 000
+    001 | subfic |       | cmpli | cmpi  | addic | addic. | addi  | addis | 001
+    010 | bc/l/a | EXT17 | b/l/a | EXT19 | rlwimi| rlwinm |       | rlwnm | 010
+    011 |  ori   | oris  | xori  | xoris | andi. | andis. | EXT30 | EXT31 | 011
+    100 |  lwz   | lwzu  | lbz   | lbzu  | stw   | stwu   | stb   | stbu  | 100
+    101 |  lhz   | lhzu  | lha   | lhau  | sth   | sthu   | lmw   | stmw  | 101
+    110 |  lfs   | lfsu  | lfd   | lfdu  | stfs  | stfsu  | stfd  | stfdu | 110
+    111 |  lq    | EXT57 | EXT58 | EXT59 | EXT60 | EXT61  | EXT62 | EXT63 | 111
+        |  000   |   001 |   010 |  011  |   100 |   101  | 110   |  111
 
 # LE/BE complications.
 
@@ -91,6 +140,19 @@ Option 3:
 
 Just as in VLE, require instructions to be in BE order. Data, which has nothing to do with instruction order, may optionally remain in LE order.
 
+## Why does VLE use a separate 64k page?
+
+VLE requires that the memory page be marked as VLE-encoded.  It also requires rhat the instructions be in BE order even when 32 bit standard opcodes are mixed in.
+
+Questions:
+
+* What would happen without the page being marked, when attempting to call ppc64le ABI code?
+* How would ppc64le code in the same page be distinguished from SVPrefix code?
+
+The answers are that it is either impossible or that it requires a special mode-switching instruction to be called on entry and exit from functions, transitioning to and from ppc64le mode.
+
+This transition may be achieved very simply by marking the 64k page.
+
 # 16 bit Compressed
 
 See [[16_bit_compressed]]