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[libreriscv.git] / openpower / sv / major_opcode_allocation.mdwn

diff --git a/openpower/sv/major_opcode_allocation.mdwn b/openpower/sv/major_opcode_allocation.mdwn
index 784790a9e6ae2c19e544b1759d1f6c3767a86335..f94733e8391450430f4ca77417ae255706fa8c30 100644 (file)
--- a/openpower/sv/major_opcode_allocation.mdwn
+++ b/openpower/sv/major_opcode_allocation.mdwn
@@ -64,6 +64,30 @@ Spare:
 
 * EXT22
 
+## C10/16 FSM
+
+    if EXT == 00/01
+         start @ 10bit
+    if state==10bit:
+         if bit15:
+             next = 16bit
+         else:
+             next = Standard
+    if state==16bit:
+         if bit0 & bit15:
+             insn = C.immediate
+         if ~bit15:
+             if ~bit0:
+                 next = Standard
+             else
+                 next = Standard.then.16bit
+
+## SV-Compressed FSM
+
+    if EXT == 09/17:
+        if bit0:
+             SV.mode = 
+
 # Major opcode map
 
 Table 9: Primary Opcode Map (opcode bits 0:5)