add ls001.po9 RFC

[libreriscv.git] / openpower / sv / major_opcode_allocation.mdwn

diff --git a/openpower/sv/major_opcode_allocation.mdwn b/openpower/sv/major_opcode_allocation.mdwn
index 31a737ab5802e02140808a54663f727b9b1e3a08..f94733e8391450430f4ca77417ae255706fa8c30 100644 (file)
--- a/openpower/sv/major_opcode_allocation.mdwn
+++ b/openpower/sv/major_opcode_allocation.mdwn
@@ -50,19 +50,44 @@ VBLOCK can be added later by using further VSX dedicated major opcodes
 
 Potential allocations:
 
-* EXT00/01 - Compressed 16 bit
-* EXT02/03 - SV-P48 / SV-C32
-* EXT04/05 - SV-P64 / SV-C48
-* EXT06/07 - ?      / SV-C64
-* EXT56/57 - SV-C32-Swizzle
-* EXT60/62 - VBLOCK
-* EXT09/17 - Predicated? SV-P48 / SV-C32
-* EXT46/47 - Predicated? SV-P64 / SV-C48
+    |  hword 0   | hword1  |  hword2    |  hword 3   |
+    EXT00/01 - C 10bit -> 16bit
+    EXT60/62 - VBLOCK
+    EXT09/17 - SV-C32 and other SV-C
+    EXT06/07 - SV-C32-Swizzle and other SV-C-Swizzle
+    EXT02/03 - SV-P48                
+    EXT04/05 - SV-P64
+    EXT56/57 - Predicated-SV-P48
+    EXT46/47 - Predicated SV-P64
 
 Spare:
 
 * EXT22
 
+## C10/16 FSM
+
+    if EXT == 00/01
+         start @ 10bit
+    if state==10bit:
+         if bit15:
+             next = 16bit
+         else:
+             next = Standard
+    if state==16bit:
+         if bit0 & bit15:
+             insn = C.immediate
+         if ~bit15:
+             if ~bit0:
+                 next = Standard
+             else
+                 next = Standard.then.16bit
+
+## SV-Compressed FSM
+
+    if EXT == 09/17:
+        if bit0:
+             SV.mode = 
+
 # Major opcode map
 
 Table 9: Primary Opcode Map (opcode bits 0:5)