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[libreriscv.git] / openpower / sv / mv.swizzle.mdwn

diff --git a/openpower/sv/mv.swizzle.mdwn b/openpower/sv/mv.swizzle.mdwn
index b6acbd3b84e29adfc218cbca51d54f789e37f0c1..0566c6f2585ce32900eaf0666550110dad5fbd97 100644 (file)
--- a/openpower/sv/mv.swizzle.mdwn
+++ b/openpower/sv/mv.swizzle.mdwn
@@ -1,5 +1,11 @@
+[[!tag standards]]
+
 # mv.swizzle
 
+Links
+
+* <https://bugs.libre-soc.org/show_bug.cgi?id=139>
+
 TODO: evaluate whether this will fit with [[mv.vec]]
 
 the encoding embeds predication into the swizzle as well as constants 1/1.0 and 0/0.0
@@ -23,12 +29,14 @@ this gives a 12 bit immediate across bits 16 to 25 and 29-30.
 
 except that the options are:
 
-* 0b1NN index 0 thru 3 to place subelement in pos XYZW
-* 0b000 to indicate "skip"
-* 0b001 to indicate "constant 0"
-* 0b010 to indicate "constant 1" (or 1.0)
-* 0b011 is not needed.
+* 0b0NN index 0 thru 3 to place subelement in pos XYZW
+* 0b110 to indicate "skip".  this is equivalent to predicate masking
+* 0b100 to indicate "constant 0"
+* 0b101 to indicate "constant 1" (or 1.0)
+* 0b111 is not needed.
+
+Evaluating efforts to encode 12 bit swizzle into less proved unsuccessful: 7^4 comes out to 2,400 which is larger than 11 bits.
 
-Evaluating efforts to encode 12 bit swizzle into less proved unsuccessful: 7^4 wcomes out to 2,400 which is larger than 11 bits
+Note that 7 options are needed (not 6) because the 7th option allows predicate masking to be encoded within the swizzle immediate.
 
 Mode M is described in [[mv.vec]] and allows for merge and split of vectors.