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[libreriscv.git] / openpower / sv / mv.vec.mdwn

diff --git a/openpower/sv/mv.vec.mdwn b/openpower/sv/mv.vec.mdwn
index 144d793de36862abf5006bbfbc3973e40966fdc2..0210b7d620eac447ee2b67b4ab259862d8a5e3ba 100644 (file)
--- a/openpower/sv/mv.vec.mdwn
+++ b/openpower/sv/mv.vec.mdwn
@@ -1,9 +1,13 @@
+[[!tag standards]]
+
 # Vector mv operations
 
-In the SIMD VSX set, section 6.8.1 and 6.8.2 p254 of v3.0B has a series of pack and unpack operations. This page covers those and more.  [[svp64]] privides the Vector Context to also add saturation as well as predication.
+In the SIMD VSX set, section 6.8.1 and 6.8.2 p254 of v3.0B has a series of pack and unpack operations. This page covers those and more.  [[svp64]] provides the Vector Context to also add saturation as well as predication.
 
 See <https://bugs.libre-soc.org/show_bug.cgi?id=230#c30>
 
+Note that some of these may be covered by [[remap]] which is described in [[sv/propagation]]
+
 # move to/from vec2/3/4
 
 Basic idea: mv operations where either the src or dest is specifically marked as having SUBVL apply to it, but, crucially, the *other* argument does *not*. Note that this is highly unusual in SimpleV, which normally only allows SUBVL to be applied uniformly across all dest and all src.
@@ -27,6 +31,24 @@ mv.destvec (leaving out elwidths and chop):
     for i in range(VL):
         regs[rd+i*SUBVL] = regs[rs+i]
 
+Note that these mv operations only become significant when elwidth is set on the vector to a small value.  SUBVL=4, src elwidth=8, dest elwidth=32 for example.
+
+intended to cover:
+
+    rd = (rs >> 0 * 8) & (2^8 - 1)
+    rd+1 = (rs >> 1 * 8) & (2^8 - 1)
+    rd+2 = (rs >> 2 * 8) & (2^8 - 1)
+    rd+3 = (rs >> 3 * 8) & (2^8 - 1)
+
+and variants involving vec3 into 32 bit (4th byte set to zero).
+TODO: include this pseudocode which shows how the vecN can do that.
+in this example RA elwidth=32 and RB elwidth=8, RB is a vec4.
+
+    for i in range(VL):
+         if predicate_bit_not_set(i) continue
+         uint8_t *start_point = (uint8_t*)(int_regfile[RA].i[i])
+         for j in range(SUBVL): # vec4
+              start_point[j] = some_op(int_regfile[RB].b[i*SUBVL + j])
 
 ## Twin Predication, saturation, swizzle, and elwidth overrides