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[libreriscv.git] / openpower / sv / mv.vec.mdwn

diff --git a/openpower/sv/mv.vec.mdwn b/openpower/sv/mv.vec.mdwn
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+[[!tag standards]]
+
 # Vector mv operations
 
 In the SIMD VSX set, section 6.8.1 and 6.8.2 p254 of v3.0B has a series of pack and unpack operations. This page covers those and more.  [[svp64]] provides the Vector Context to also add saturation as well as predication.
 
 See <https://bugs.libre-soc.org/show_bug.cgi?id=230#c30>
 
+Note that some of these may be covered by [[remap]] which is described in [[sv/propagation]]
+
 # move to/from vec2/3/4
 
 Basic idea: mv operations where either the src or dest is specifically marked as having SUBVL apply to it, but, crucially, the *other* argument does *not*. Note that this is highly unusual in SimpleV, which normally only allows SUBVL to be applied uniformly across all dest and all src.