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[libreriscv.git] / openpower / sv / normal.mdwn

diff --git a/openpower/sv/normal.mdwn b/openpower/sv/normal.mdwn
index 7d1185c96694e9d6291ee60c64c726cc55a3c370..4283e07690dce681b019255ef3061a9f86a7e505 100644 (file)
--- a/openpower/sv/normal.mdwn
+++ b/openpower/sv/normal.mdwn
@@ -43,22 +43,21 @@ The Mode table for Arithmetic and Logical operations
 | 0-1 |  2  |  3   4  |  description              |
 | --- | --- |---------|-------------------------- |
 | 00  |   0 |  dz  sz | normal mode                      |
-| 00  |   1 | 0  RG   | scalar reduce mode (mapreduce), SUBVL=1 |
-| 00  |   1 | 1  /    | parallel reduce mode (mapreduce), SUBVL=1 |
-| 00  |   1 | SVM RG  | subvector reduce mode, SUBVL>1   |
+| 00  |   1 | 0  RG   | scalar reduce mode (mapreduce) |
+| 00  |   1 | 1  /    | parallel reduce mode (mapreduce) |
 | 01  | inv | CR-bit  | Rc=1: ffirst CR sel              |
 | 01  | inv | VLi RC1 |  Rc=0: ffirst z/nonz |
 | 10  |   N | dz   sz |  sat mode: N=0/1 u/s |
 | 11  | inv | CR-bit  |  Rc=1: pred-result CR sel |
-| 11  | inv | dz  RC1 |  Rc=0: pred-result z/nonz |
+| 11  | inv | zz  RC1 |  Rc=0: pred-result z/nonz |
 
 Fields:
 
 * **sz / dz**  if predication is enabled will put zeros into the dest (or as src in the case of twin pred) when the predicate bit is zero.  otherwise the element is ignored or skipped, depending on context.
+* **zz**: both sz and dz are set equal to this flag
 * **inv CR bit** just as in branches (BO) these bits allow testing of a CR bit and whether it is set (inv=0) or unset (inv=1)
 * **RG** inverts the Vector Loop order (VL-1 downto 0) rather
 than the normal 0..VL-1
-* **SVM** sets "subvector" reduce mode
 * **N** sets signed/unsigned saturation.
 * **RC1** as if Rc=1, stores CRs *but not the result*
 * **VLi** VL inclusive: in fail-first mode, the truncation of
@@ -107,7 +106,7 @@ dest elwidth.
 
 *Programmer's Note: Post-analysis of the Vector of CRs to find out if any given element hit
 saturation may be done using a mapreduced CR op (cror), or by using the
-new crweird instruction with Rc=1, which will transfer the required
+new crrweird instruction with Rc=1, which will transfer the required
 CR bits to a scalar integer and update CR0, which will allow testing
 the scalar integer for nonzero.  see [[sv/cr_int_predication]]*
 
@@ -158,11 +157,12 @@ of strncpy, to include the terminating zero.
 
 In CR-based data-driven fail-on-first there is only the option to select
 and test one bit of each CR (just as with branch BO).  For more complex
-tests this may be insufficient.  If that is the case, a vectorised crops
+tests this may be insufficient.  If that is the case, a vectorised crop
 (crand, cror) may be used, and ffirst applied to the crop instead of to
-the arithmetic vector.
+the arithmetic vector. Note that crops are covered by 
+the [[sv/cr_ops]] Mode format.
 
-One extremely important aspect of ffirst is:
+Two extremely important aspects of ffirst are:
 
 * LDST ffirst may never set VL equal to zero.  This because on the first
   element an exception must be raised "as normal".
@@ -173,7 +173,12 @@ One extremely important aspect of ffirst is:
   vectorised operations are effectively `nops` which is
   *precisely the desired and intended behaviour*.
 
-CR-based data-dependent first on the other hand MUST not truncate VL
+The second crucial aspect, compared to LDST Ffirst:
+
+* LD/ST Failfirst may (beyond the initial first element
+  conditions) truncate VL for any architecturally
+  suitable reason.
+* CR-based data-dependent first on the other hand MUST NOT truncate VL
 arbitrarily to a length decided by the hardware: VL MUST only be
 truncated based explicitly on whether a test fails.
 This because it is a precise test on which algorithms