whoops headings

[libreriscv.git] / openpower / sv / normal.mdwn

diff --git a/openpower/sv/normal.mdwn b/openpower/sv/normal.mdwn
index e913b1253ca587d29c7fa7b090fe1cefef1c504f..8e3a539a64328e8806e927b15156f62ad6cc7db4 100644 (file)
--- a/openpower/sv/normal.mdwn
+++ b/openpower/sv/normal.mdwn
@@ -150,7 +150,8 @@ Easy examples include Reduction on Logical OR or AND operations.*
 **Horizontal Parallelism Hint**
 
 `SVSTATE.hphint` declares to hardware that groups of elements up to this
-size are 100% independent.  With Reduction literally creating Dependency
+size are 100% independent (free of all Hazards inter-element but not inter-group).
+With Reduction literally creating Dependency
 Hazards on every element-level sub-instruction it is pretty clear that setting
 `hphint` *at all* would cause data corruption.  However `sv.add *r0, *r4, *r0`
 for example clearly leaves room for four parallel elements. Programmers must
@@ -234,8 +235,7 @@ Two extremely important aspects of ffirst are:
 * LDST ffirst may never set VL equal to zero. This because on the first
   element an exception must be raised "as normal".
 * CR-based data-dependent ffirst on the other hand **can** set VL equal
-  to zero. This is the only means in the entirety of SV that VL may be set
-  to zero (with the exception of via the SV.STATE SPR).  When VL is set
+  to zero.  When VL is set
   zero due to the first element failing the CR bit-test, all subsequent
   vectorised operations are effectively `nops` which is
   *precisely the desired and intended behaviour*.