# SV Overview
-**SV is in DRAFT STATUS**. SV has not yet been submitted to the OpenPOWER Foundation ISA WG for review.
+**SV is in DRAFT STATUS**. SV has not yet been submitted to the OpenPOWER
+Foundation ISA WG for review.
This document provides an overview and introduction as to why SV (a
-[[!wikipedia Cray]]-style Vector augmentation to [[!wikipedia OpenPOWER]]) exists, and how it works.
+[[!wikipedia Cray]]-style Vector augmentation to
+[[!wikipedia OpenPOWER]]) exists, and how it works.
**Sponsored by NLnet under the Privacy and Enhanced Trust Programme**
Links:
* This page: [http://libre-soc.org/openpower/sv/overview](http://libre-soc.org/openpower/sv/overview)
-* [FOSDEM2021 SimpleV for OpenPOWER](https://fosdem.org/2021/schedule/event/the_libresoc_project_simple_v_vectorisation/)
+* [FOSDEM2021 SimpleV for Power ISA](https://fosdem.org/2021/schedule/event/the_libresoc_project_simple_v_vectorization/)
* FOSDEM2021 presentation <https://www.youtube.com/watch?v=FS6tbfyb2VA>
* [[discussion]] and
[bugreport](https://bugs.libre-soc.org/show_bug.cgi?id=556)
through an ISA revision. The opcode proliferation, at O(N^6), inexorably
spirals out of control in the ISA, detrimentally impacting the hardware,
the software, the compilers and the testing and compliance. Here are
-the typical dimensions that result in such massive proliferation:
+the typical dimensions that result in such massive proliferation,
+based on mass-volume DSPs and Micro-Processors:
* Operation (add, mul)
* bitwidth (8, 16, 32, 64, 128)
increase using "tagging" (similar to how x86 originally extended
registers from 32 to 64 bit).
+{ width=40% height=20% }
+
## SV
The fundamentals are (just like x86 "REP"):
* The Program Counter (PC) gains a "Sub Counter" context (Sub-PC)
-* Vectorisation pauses the PC and runs a Sub-PC loop from 0 to VL-1
+* Vectorization pauses the PC and runs a Sub-PC loop from 0 to VL-1
(where VL is Vector Length)
* The [[Program Order]] of "Sub-PC" instructions must be preserved,
just as is expected of instructions ordered by the PC.
* Once the loop is completed *only then* is the Program Counter
allowed to move to the next instruction.
-
+{ width=40% height=40% }
Hardware (and simulator) implementors are free and clear to implement this
as literally a for-loop, sitting in between instruction decode and issue.
out-of-order execution, although it is strongly recommended to add
predication capability directly into SIMD backend units.
-In OpenPOWER ISA v3.0B pseudo-code form, an ADD operation, assuming both
-source and destination have been "tagged" as Vectors, is simply:
+A typical Cray-style Scalable Vector ISA (where a SIMD one has a fixed
+non-negotiable static parameter instead of a runtime-dynamic VL)
+performs its arithmetic as:
+
+ for i = 0 to VL-1:
+ VPR(RT)[i] = VPR[RA][i] + VPR(RB)[i]
+
+In Power ISA v3.0B pseudo-code form, an ADD operation in Simple-V,
+assuming both source and destination have been "tagged" as Vectors,
+is simply:
for i = 0 to VL-1:
GPR(RT+i) = GPR(RA+i) + GPR(RB+i)
RISC-V RVV as of version 0.9 is over 188 instructions (more than the
rest of RV64G combined: 80 for RV64G and 27 for C). Over 95% of that
-functionality is added to OpenPOWER v3 0B, by SimpleV augmentation,
+functionality is added to Power v3.0B, by SimpleV augmentation,
with around 5 to 8 instructions.
-Even in OpenPOWER v3.0B, the Scalar Integer ISA is around 150
+Even in Power ISA v3.0B, the Scalar Integer ISA is around 150
instructions, with IEEE754 FP adding approximately 80 more. VSX, being
based on SIMD design principles, adds somewhere in the region of 600 more.
SimpleV again provides over 95% of VSX functionality, simply by augmenting
-the *Scalar* OpenPOWER ISA, and in the process providing features such
+the *Scalar* Power ISA, and in the process providing features such
as predication, which VSX is entirely missing.
AVX512, SVE2, VSX, RVV, all of these systems have to provide different
even provides a mini mask regfile, followed by explicit instructions
that handle operations on each of them *and map between all of them*.
SV simply not only uses the existing scalar regfiles (including CRs),
-but because operations exist within OpenPOWER to cover interactions
+but because operations exist within Power ISA to cover interactions
between the scalar regfiles (`mfcr`, `fcvt`) there is very little that
needs to be added.
* Compacted operations into registers (normally only provided by SIMD)
* Fail-on-first (introduced in ARM SVE2)
* A new concept: Data-dependent fail-first
-* Condition-Register based *post-result* predication (also new)
* A completely new concept: "Twin Predication"
* vec2/3/4 "Subvectors" and Swizzling (standard fare for 3D)
-All of this is *without modifying the OpenPOWER v3.0B ISA*, except to add
+All of this is *without modifying the Power v3.0B ISA*, except to add
"wrapping context", similar to how v3.1B 64 Prefixes work.
# Adding Scalar / Vector
that loop size to one.
The important insight from the above is that, strictly speaking, Simple-V
-is not really a Vectorisation scheme at all: it is more of a hardware
+is not really a Vectorization scheme at all: it is more of a hardware
ISA "Compression scheme", allowing as it does for what would normally
require multiple sequential instructions to be replaced with just one.
This is where the rule that Program Order must be preserved in Sub-PC
execution derives from. However in other ways, which will emerge below,
the "tagging" concept presents an opportunity to include features
definitely not common outside of Vector ISAs, and in that regard it's
-definitely a class of Vectorisation.
+definitely a class of Vectorization.
## Register "tagging"
The reason for using so few bits is because there are up to *four*
registers to mark in this way (`fma`, `isel`) which starts to be of
concern when there are only 24 available bits to specify the entire SV
-Vectorisation Context. In fact, for a small subset of instructions it
+Vectorization Context. In fact, for a small subset of instructions it
is just not possible to tag every single register. Under these rare
circumstances a tag has to be shared between two registers.
principle, which takes into account the fact that each CR may be bit-level
addressed by Condition Register operations.
-Readers familiar with OpenPOWER will know of Rc=1 operations that create
+Readers familiar with the Power ISA will know of Rc=1 operations that create
an associated post-result "test", placing this test into an implicit
Condition Register. The original researchers who created the POWER ISA
chose CR0 for Integer, and CR1 for Floating Point. These *also become
-Vectorised* - implicitly - if the associated destination register is
-also Vectorised. This allows for some very interesting savings on
+Vectorized* - implicitly - if the associated destination register is
+also Vectorized. This allows for some very interesting savings on
instruction count due to the very same CR Vectors being predication masks.
# Adding single predication
function op_add(RT, RA, RB) # add not VADD!
int id=0, irs1=0, irs2=0;
- predval = get_pred_val(FALSE, rd);
+ predval = get_pred_val(FALSE, RT); # dest mask
for i = 0 to VL-1:
if (predval & 1<<i) # predication bit test
ireg[RT+id] <= ireg[RA+irs1] + ireg[RB+irs2];
If all three registers are marked as Vector then the "traditional"
predicated Vector behaviour is provided. Yet, just as before, all other
options are still provided, right the way back to the pure-scalar case,
-as if this were a straight OpenPOWER v3.0B non-augmented instruction.
+as if this were a straight Power ISA v3.0B non-augmented instruction.
Single Predication therefore provides several modes traditionally seen
in Vector ISAs:
function op_add(RT, RA, RB) # add not VADD!
int id=0, irs1=0, irs2=0;
- predval = get_pred_val(FALSE, rd);
+ predval = get_pred_val(FALSE, RT); # dest pred
for i = 0 to VL-1:
if (predval & 1<<i) # predication bit test
ireg[RT+id] <= ireg[RA+irs1] + ireg[RB+irs2];
32 for integer, and FP16 and FP32 for IEEE754 (with BF16 to be added in
the future).
-This presents a particularly intriguing conundrum given that the OpenPOWER
+This presents a particularly intriguing conundrum given that the Power
Scalar ISA was never designed with for example 8 bit operations in mind,
let alone Vectors of 8 bit.
uint8_t b[0]; // array of type uint8_t
uint16_t s[0]; // array of LE ordered uint16_t
uint32_t i[0];
- uint64_t l[0]; // default OpenPOWER ISA uses this
+ uint64_t l[0]; // default Power ISA uses this
} reg_t;
reg_t int_regfile[128]; // SV extends to 128 regs
"register" but that from that location onwards the elements *overlap
subsequent registers*.
-{ width=40% }
+{ width=40% height=40% }
Here is another way to view the same concept, bearing in mind that it
is assumed a LE memory order:
That decision was - arbitrarily - LE mode. Actually it wasn't arbitrary
at all: it was such hell to implement BE supported interpretations of CRs
and LD/ST in LibreSOC, based on a terse spec that provides insufficient
-clarity and assumes significant working knowledge of OpenPOWER, with
+clarity and assumes significant working knowledge of the Power ISA, with
arbitrary insertions of 7-index here and 3-bitindex there, the decision
to pick LE was extremely easy.
is VGATHER (and VSCATTER): moving registers by specifying a vector of
register indices (`regs[rd] = regs[regs[rs]]` in a loop). This one is
tricky because it typically does not exist in standard scalar ISAs.
-If it did it would be called [[sv/mv.x]]. Once Vectorised, it's a
+If it did it would be called [[sv/mv.x]]. Once Vectorized, it's a
VGATHER/VSCATTER.
-# CR predicate result analysis
-
-OpenPOWER has Condition Registers. These store an analysis of the result
-of an operation to test it for being greater, less than or equal to zero.
-What if a test could be done, similar to branch BO testing, which hooked
-into the predication system?
-
- for i in range(VL):
- # predication test, skip all masked out elements.
- if predicate_masked_out(i): continue # skip
- result = op(iregs[RA+i], iregs[RB+i])
- CRnew = analyse(result) # calculates eq/lt/gt
- # Rc=1 always stores the CR
- if RC1 or Rc=1: crregs[offs+i] = CRnew
- if RC1: continue # RC1 mode skips result store
- # now test CR, similar to branch
- if CRnew[BO[0:1]] == BO[2]:
- # result optionally stored but CR always is
- iregs[RT+i] = result
-
-Note that whilst the Vector of CRs is always written to the CR regfile,
-only those result elements that pass the BO test get written to the
-integer regfile (when RC1 mode is not set). In RC1 mode the CR is always
-stored, but the result never is. This effectively turns every arithmetic
-operation into a type of `cmp` instruction.
-
-Here for example if FP overflow occurred, and the CR testing was carried
-out for that, all valid results would be stored but invalid ones would
-not, but in addition the Vector of CRs would contain the indicators of
-which ones failed. With the invalid results being simply not written
-this could save resources (save on register file writes).
-
-Also expected is, due to the fact that the predicate mask is effectively
-ANDed with the post-result analysis as a secondary type of predication,
-that there would be savings to be had in some types of operations where
-the post-result analysis, if not included in SV, would need a second
-predicate calculation followed by a predicate mask AND operation.
-
-Note, hilariously, that Vectorised Condition Register Operations (crand,
-cror) may also have post-result analysis applied to them. With Vectors
-of CRs being utilised *for* predication, possibilities for compact and
-elegant code begin to emerge from this innocuous-looking addition to SV.
-
# Exception-based Fail-on-first
-One of the major issues with Vectorised LD/ST operations is when a
+One of the major issues with Vectorized LD/ST operations is when a
batch of LDs cross a page-fault boundary. With considerable resources
being taken up with in-flight data, a large Vector LD being cancelled
or unable to roll back is either a detriment to performance or can cause
# Data-dependent fail-first
-This is a minor variant on the CR-based predicate-result mode. Where
-pred-result continues with independent element testing (any of which may
-be parallelised), data-dependent fail-first *stops* at the first failure:
+Data-dependent fail-first *stops* at the first failure:
if Rc=0: BO = inv<<2 | 0b00 # test CR.eq bit z/nz
for i in range(VL):
CRnew = analyse(result) # calculates eq/lt/gt
# now test CR, similar to branch
if CRnew[BO[0:1]] != BO[2]:
- VL = i # truncate: only successes allowed
+ VL = i+VLi # truncate: only successes allowed
break
# test passed: store result (and CR?)
if not RC1: iregs[RT+i] = result
the actual calculation.
The only minor downside here though is the change to VL, which in some
-implementations may cause pipeline stalls. This was one of the reasons
-why CR-based pred-result analysis was added, because that at least is
-entirely paralleliseable.
+implementations may cause pipeline stalls.
# Vertical-First Mode
+{ width=40% height=40% }
+
This is a relatively new addition to SVP64 under development as of
July 2021. Where Horizontal-First is the standard Cray-style for-loop,
Vertical-First typically executes just the **one** scalar element
-in each Vectorised operation. That element is selected by srcstep
+in each Vectorized operation. That element is selected by srcstep
and dststep *neither of which are changed as a side-effect of execution*.
Illustrating this in pseodocode, with a branch/loop.
To create loops, a new instruction `svstep` must be called,
beq loop
```
-
-
Three examples are illustrated of different types of Scalar-Vector
operations. Note that in its simplest form **only one** element is
executed per instruction **not** multiple elements per instruction.
and what's in it? Bearing in mind that this requires OPF review, the
current draft is at the [[sv/svp64]] page, and includes space for all the
different modes, the predicates, element width overrides, SUBVL and the
-register extensions, in 24 bits. This just about fits into an OpenPOWER
+register extensions, in 24 bits. This just about fits into a Power
v3.1B 64 bit Prefix by borrowing some of the Reserved Encoding space.
-The v3.1B suffix - containing as it does a 32 bit OpenPOWER instruction -
+The v3.1B suffix - containing as it does a 32 bi Power instruction -
aligns perfectly with SV.
Further reading is at the main [[SV|sv]] page.
# Conclusion
-Starting from a scalar ISA - OpenPOWER v3.0B - it was shown above that,
+Starting from a scalar ISA - Power v3.0B - it was shown above that,
with conceptual sub-loops, a Scalar ISA can be turned into a Vector one,
by embedding Scalar instructions - unmodified - into a Vector "context"
using "Prefixing". With careful thought, this technique reaches 90%
par with good Vector ISAs, increasing to 95% with the addition of a
-mere handful of additional context-vectoriseable scalar instructions
+mere handful of additional context-vectorizeable scalar instructions
([[sv/mv.x]] amongst them).
What is particularly cool about the SV concept is that custom extensions
and research need not be concerned about inventing new Vector instructions
and how to get them to interact with the Scalar ISA: they are effectively
one and the same. Any new instruction added at the Scalar level is
-inherently and automatically Vectorised, following some simple rules.
+inherently and automatically Vectorized, following some simple rules.
projects / libreriscv.git / blobdiff