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[libreriscv.git] / openpower / sv / overview.mdwn

diff --git a/openpower/sv/overview.mdwn b/openpower/sv/overview.mdwn
index c2d3e21a788c08729fc2217db20dbc32da2c9498..e752c3145a21bc953a763526c6e0efb245838143 100644 (file)
--- a/openpower/sv/overview.mdwn
+++ b/openpower/sv/overview.mdwn
@@ -11,15 +11,17 @@ SIMD, the primary method for easy parallelism of the
 past 30 years in Computer Architectures, is [known to be
 harmful](https://www.sigarch.org/simd-instructions-considered-harmful/).
 SIMD provides a seductive simplicity that is easy to implement in
-hardware.  Even with predication added, SIMD only becomes more and
+hardware.  With each doubling in width it promises increases in raw performance without the complexity of either multi-issue or out-of-order execution.
+
+Unfortunately, even with predication added, SIMD only becomes more and
 more problematic with each power of two SIMD width increase introduced
 through an ISA revision.  The opcode proliferation, at O(N^6), inexorably
 spirals out of control in the ISA, detrimentally impacting the hardware,
-the software and the compilers.
+the software, the compilers and the testing and compliance.
 
 Cray-style variable-length Vectors on the other hand result in
 stunningly elegant and small loops, exceptionally high data throughput
-per instruction, with no alarmingly high setup and cleanup code, where
+per instruction (by one *or greater* orders of magnitude than SIMD), with no alarmingly high setup and cleanup code, where
 at the hardware level the microarchitecture may execute from one element
 right the way through to tens of thousands at a time, yet the executable
 remains exactly the same and the ISA remains clear, true to the RISC