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[libreriscv.git] / openpower / sv / propagation.mdwn

diff --git a/openpower/sv/propagation.mdwn b/openpower/sv/propagation.mdwn
index 16bf2b884dbd91861c6648592156920e1308b342..1d6e8242a66e5e39bff09f1d0a5cf3da1e0b3023 100644 (file)
--- a/openpower/sv/propagation.mdwn
+++ b/openpower/sv/propagation.mdwn
@@ -49,8 +49,8 @@ swizzle. Their format is as follows when stored in SPRs:
 | 0000 | 0000   | `RM[0:23]`  |  [[sv/svp64]] RM |
 | 0000 | 0001   |`setvl[0:23]`|  [[sv/setvl]] VL |
 | 0001 | 0 mask | swiz1 swiz2 |  swizzle  |
-| 0010 | brev   | sh0-3 ms0-3 |  [Remap](sv/remap)    |
-| 0011 | brev   | sh0-3 ms0-3 |  [SubVL Remap](sv/remap)    |
+| 0010 | brev   | sh0-4 ms0-5 |  [Remap](sv/remap)    |
+| 0011 | brev   | sh0-4 ms0-4 |  [SubVL Remap](sv/remap)    |
 
 There are 4 64 bit SPRs used for storing Context, and the data is stored
 as follows:
@@ -58,13 +58,20 @@ as follows:
 * 7 32 bit contexts are stored, each indexed from 0b001 to 0b111,
   2 per 64 bit SPR and 1 in the 4th.
 * Starting from bit 32 of the 4th SPR, in batches of 40 bits the Shift
-  Registers are stored.
-
-               0            31 32         63
-    SVREMAP0   context 0       context 1
-    SVREMAP1   context 2       context 3
-    SVREMAP2   context 4       context 5
-    SVREMAP3   context 6       
+  Registers (bit-level FIFOs) are stored.
+
+```
+             0            31 32         63
+    SVCTX0   context 0       context 1
+    SVCTX1   context 2       context 3
+    SVCTX2   context 4       context 5
+    SVCTX3   context 6       FIFO0[0..31]
+    SVCTX4   FIFO0[32:39]   FIFO1[0:39] FIFO2[0:15]
+    SVCTX5   FIFO2[16:39]   FIFO3[0:39] FIFO4[0:7]
+    SVCTX5   FIFO4[8:39]    FIFO5[0:39] FIFO5[0:15]
+    SVCTX6   FIFO5[16:39]   FIFO6[0:39] FIFO7[0:7
+    SVCTX7   FIFO7[16:39]
+```
 
 When each LSB is nonzero in any one of the seven Shift Registers
 the corresponding Contexts are looked up and merged (ORed) together.
@@ -201,24 +208,14 @@ vec2/3/4, that would be handled by swizzle reordering):
 
 Again it is the 24 bit `RM` that is interpreted differently:
 
-| 0...7 | 8....23 |
-| ----- | ------- |
-| sh0-3 | mask0-3 |
-
-The shape indices 0-3 are numbered 0-3 whilst the masks are bitmasks
-that indicate src or dest to which the associated shape (0-3) is to
-be applied.  A zero mask indicates that the Shape is not to be applied.
-Note that whilst the masks are unary encoded the Shape indices sh0-3
-are not: this must be taken into consideration when ORing occurs.
-
-The mask is encoded as follows:
-
-* bit 0 indicates that the first svp64 EXTRA field is reshaped
-* bit 1 indicates that the second svp64 EXTRA field is reshaped
-* bit 2 indicates that the third sv64 EXTRA field is reshaped
-* bit 3 indicates that the fourth svp64 EXTRA field reshaped
+| 0  | 2  | 4  | 6  | 8  | 10.14 | 15..23 |
+| -- | -- | -- | -- | -- | ----- | ------ |
+|mi0 |mi1 |mi2 |mo0 |mo1 | en0-4 | rsv    |
 
-This allows even instructions that have 2 destination registers to be reshaped.
+si0-2 and so0-1 each select SVSHAPE0-3 to apply to a given register.
+si0-2 apply to RA, RB, RC respectively, as input registers, and
+likewise so0-1 apply to output registers. en0-4 indicate whether the
+SVSHAPE is actively applied or not.
 
 # setvl