replace "Defined word" with "Defined Word-instruction"

[libreriscv.git] / openpower / sv / remap.mdwn

diff --git a/openpower/sv/remap.mdwn b/openpower/sv/remap.mdwn
index 9b6a5a82c004aa89505c1966d1f13accd4489a2b..545be7ecf7bb91a68317feb7a25ae6f9b1da2e38 100644 (file)
--- a/openpower/sv/remap.mdwn
+++ b/openpower/sv/remap.mdwn
@@ -329,7 +329,7 @@ Interrupts and exceptions
 can therefore also be precise.  The final result will be in the first
 non-predicate-masked-out destination element, but due again to
 the deterministic schedule programmers may find uses for the intermediate
-results, even for non-commutative Defined Word operations.
+results, even for non-commutative Defined Word-instruction operations.
 Additionally, because the intermediate results are always written out
 it is possible to service Precise Interrupts without affecting latency
 (a common limitation of Vector ISAs implementing explicit
@@ -435,7 +435,7 @@ not work.
 
 To achieve Sub-Vector Horizontal Reduction, Pack/Unpack should be enabled,
 which will turn the Schedule around such that issuing of the Scalar
-Defined Words is done with SUBVL looping as the inner loop not the
+Defined Word-instructions is done with SUBVL looping as the inner loop not the
 outer loop. Rc=1 with Sub-Vectors (SUBVL=2,3,4) is `UNDEFINED` behaviour.
 
 *Programmer's Note: Overwrite Parallel Reduction with Sub-Vectors