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[libreriscv.git] / openpower / sv / remap.mdwn

diff --git a/openpower/sv/remap.mdwn b/openpower/sv/remap.mdwn
index 99fb0a1f141a94a187bbc310369a429be51008f0..a0a96405063ae7ee10fed224beca45a6d312c5a8 100644 (file)
--- a/openpower/sv/remap.mdwn
+++ b/openpower/sv/remap.mdwn
@@ -63,8 +63,8 @@ SVSHAPE is actively applied or not.
 There is also a corresponding SVRM-Form for the svremap
 instruction which matches the above SPR:
 
-    |0     |6     |11  |13   |15   |17   |19   |21    |26     |31 |
-    | PO   | SVme |mi0 | mi1 | mi2 | mo0 | mo1 | rsvd | XO    | / |
+    |0     |6     |11  |13   |15   |17   |19   |21    | 22    |26     |31 |
+    | PO   | SVme |mi0 | mi1 | mi2 | mo0 | mo1 | pst  | rsvd | XO    | / |
 
 # SHAPE 1D/2D/3D vector-matrix remapping SPRs
 
@@ -154,7 +154,7 @@ pipeline overlaps.  Out-of-order / Superscalar micro-architectures with
 register-renaming will have an easier time dealing with this than
 DSP-style SIMD micro-architectures.
 
-## TEMPORARY HELPER
+## svstate instruction
 
 Please note: this is **not** intended for production.  It sets up
 (overwrites) all required SVSHAPE SPRs and indicates that the
@@ -163,16 +163,18 @@ assuming that instruction is of the form FRT,FRA,FRC,FRB.
 
 Form: SVM-Form SV "Matrix" Form (see [[isatables/fields.text]])
 
-| 0.5|6.10  |11.15  |16..20 | 21..25 | 26..30 |31|  name    |
-| -- | --   | ---   | ----- | ------ | ------ |--| -------- |
-|OPCD| SVxd | SVyd  | SVzd  | SVRM   | XO     |/ | svremap  |
+| 0.5|6.10  |11.15  |16..20 | 21..25 | 25 | 26..30 |31|  name    |
+| -- | --   | ---   | ----- | ------ | -- | ------ |--| -------- |
+|OPCD| SVxd | SVyd  | SVzd  | SVRM   | vf | XO     |/ | svstate  |
+
 
 Fields:
 
 * **SVxd** - SV REMAP "xdim"
 * **SVyd** - SV REMAP "ydim"
-* **SVMM** - SV REMAP Mode (currently 0b00000 only)
-* **XO** - standard 10-bit XO field
+* **SVMM** - SV REMAP Mode (0b00000 for Matrix, 0b00001 for FFT)
+* **vf** - sets "Vertical-First" mode
+* **XO** - standard 5-bit XO field
 
 # 4x4 Matrix to vec4 Multiply Example