(no commit message)

[libreriscv.git] / openpower / sv / rfc / ls011.mdwn

diff --git a/openpower/sv/rfc/ls011.mdwn b/openpower/sv/rfc/ls011.mdwn
index 516b012d4cb52c030533f4869f2423ca5cc43332..4cb05c3e9d4b11bdf3eb764ce4e8d94c59c75f7f 100644 (file)
--- a/openpower/sv/rfc/ls011.mdwn
+++ b/openpower/sv/rfc/ls011.mdwn
@@ -115,5 +115,192 @@ where the same pseudocode for `lbzu` is:
     RT <- ([0] * (XLEN-8)) || MEM(EA, 1)  # load from RA+D
     RA <- EA                              # and update RA 
 ```
+-----
+
+\newpage{}
+
+# Fixed-point Load with Post-Update
+
+Add the following additional Section to Fixed-Point Load Book I
+
+## Load Byte and Zero with Post-Update
+
+D-Form
+
+* lbzup RT,D(RA)
+
+Pseudo-code:
+
+    EA <- (RA)
+    RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
+    RA <- (RA) + EXTS(D)
+
+Special Registers Altered:
+
+    None
+
+## Load Byte and Zero with Post-Update Indexed
+
+X-Form
+
+* lbzupx RT,RA,RB
+
+Pseudo-code:
+
+    EA <- (RA)
+    RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
+    RA <- (RA) + (RB)
+
+Special Registers Altered:
+
+    None
+
+## Load Halfword and Zero with Post-Update
+
+D-Form
+
+* lhzup RT,D(RA)
+
+Pseudo-code:
+
+    EA <- (RA)
+    RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
+    RA <- (RA) + EXTS(D)
+
+Special Registers Altered:
+
+    None
+
+## Load Halfword and Zero with Post-Update Indexed
+
+X-Form
+
+* lhzupx RT,RA,RB
+
+Pseudo-code:
+
+    EA <- (RA)
+    RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
+    RA <- (RA) + (RB)
+
+Special Registers Altered:
+
+    None
+
+## Load Halfword Algebraic with Post-Update
+
+D-Form
+
+* lhaup RT,D(RA)
+
+Pseudo-code:
+
+    EA <- (RA)
+    RT <- EXTS(MEM(EA, 2))
+    RA <- (RA) + EXTS(D)
+
+Special Registers Altered:
+
+    None
+
+## Load Halfword Algebraic with Post-Update Indexed
+
+X-Form
+
+* lhaupx RT,RA,RB
+
+Pseudo-code:
+
+    EA <- (RA)
+    RT <- EXTS(MEM(EA, 2))
+    RA <- (RA) + (RB)
+
+Special Registers Altered:
+
+    None
+
+## Load Word and Zero with Post-Update
+
+D-Form
+
+* lwzup RT,D(RA)
+
+Pseudo-code:
+
+    EA <- (RA)
+    RT <- [0]*32 || MEM(EA, 4)
+    RA <- (RA) + EXTS(D)
+
+Special Registers Altered:
+
+    None
+
+## Load Word and Zero with Post-Update Indexed
+
+X-Form
+
+* lwzupx RT,RA,RB
+
+Pseudo-code:
+
+    EA <- (RA)
+    RT <- [0] * 32 || MEM(EA, 4)
+    RA <- (RA) + (RB)
+
+Special Registers Altered:
+
+    None
+
+## Load Word Algebraic with Post-Update Indexed
+
+X-Form
+
+* lwaupx RT,RA,RB
+
+Pseudo-code:
+
+    EA <- (RA)
+    RT <- EXTS(MEM(EA, 4))
+    RA <- (RA) + (RB)
+
+Special Registers Altered:
+
+    None
+
+## Load Doubleword with Post-Update Indexed
+
+DS-Form
+
+* ldup RT,DS(RA)
+
+Pseudo-code:
+
+    EA <- (RA)
+    RT <- MEM(EA, 8)
+    RA <- (RA) + EXTS(DS || 0b00)
+
+Special Registers Altered:
+
+    None
+
+## Load Doubleword with Post-Update Indexed
+
+X-Form
+
+* ldupx RT,RA,RB
+
+Pseudo-code:
+
+    EA <- (RA)
+    RT <- MEM(EA, 8)
+    RA <- (RA) + (RB)
+
+Special Registers Altered:
+
+    None
+
+-----
+
+\newpage{}
 
 [[!tag opf_rfc]]