(no commit message)

[libreriscv.git] / openpower / sv / setvl.mdwn

diff --git a/openpower/sv/setvl.mdwn b/openpower/sv/setvl.mdwn
index 17aaf651841bfa9aab073da221a51460b8567c96..b40aa46e46daad98a6e0807315aeb775b3878530 100644 (file)
--- a/openpower/sv/setvl.mdwn
+++ b/openpower/sv/setvl.mdwn
@@ -4,20 +4,23 @@ See links:
 
 * <http://lists.libre-soc.org/pipermail/libre-soc-dev/2020-November/001366.html>
 * <https://bugs.libre-soc.org/show_bug.cgi?id=535>
+* <https://bugs.libre-soc.org/show_bug.cgi?id=568> TODO
 * <https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#vsetvlivsetvl-instructions>
 
 Use of setvl results in changes to the MVL, VL and STATE SPRs. see [[sv/sprs]]♧
 
 # Format
 
-| 0.5|6.10|11.15|16.20| 21..24.25  | 26...30 |31|  name   |
+*(Allocation of opcode TBD pending OPF ISA WG approval)*
+
+| 0.5|6.10|11.15|16.20| 21..24.25   | 26...30 |31|  name   |
 | -- | -- | --- | --- | ----------- | ------- |--| ------- |
 | 19 | RT | RA  |     | XO[0:4]     | XO[5:9] |Rc| XL-Form |
 | 19 | RT | RA  | imm | i //  vs ms | NNNNN   |Rc| setvl   |
 
 Note that imm spans 7 bits (16 to 22), and that bit 22 is reserved and must be zero.  Setting bit 22 causes an illegal exception.
 
-Note that VL and MVL start from **one** i.e. that an immediate value of zero will result in VL/MVL being set to 1.  0b111111 results in VL/MVL being set to 64. This is because setting VL/MVL to 1 results in "scalar identity" behaviour, where setting VL/MVL to 0 would result in all Vector operations becoming nop.  If this is truly desired (nop behaviour) then setting VL and MVL to zero be done via the [[SV SPRs|sv/sprs]]
+Note that in immediate setting mode VL and MVL start from **one** i.e. that an immediate value of zero will result in VL/MVL being set to 1.  0b111111 results in VL/MVL being set to 64. This is because setting VL/MVL to 1 results in "scalar identity" behaviour, where setting VL/MVL to 0 would result in all Vector operations becoming `nop`.  If this is truly desired (nop behaviour) then setting VL and MVL to zero is to be done via the [[SV SPRs|sv/sprs]]
 
 Note that setmvli is a pseudo-op, based on RA/RT=0, and setvli likewise
 
@@ -29,11 +32,11 @@ Note that setmvli is a pseudo-op, based on RA/RT=0, and setvli likewise
     // instruction fields:
     rd = get_rt_field();         // bits 6..10
     ra = get_ra_field();         // bits 11..15
-    // add one. MVL/VL=1..64 not 0..63
-    vlimmed = get_immed_field()+1; //  16..22
     vs = get_vs_field();         // bit 24
     ms = get_ms_field();         // bit 25
     Rc = get_Rc_field();         // bit 31
+    // add one. MVL/VL=1..64 not 0..63
+    vlimmed = get_immed_field()+1; //  16..22
 
     // set VL (or not).
     // 3 options: from SPR, from immed, from ra
@@ -101,7 +104,7 @@ Note that setmvli is a pseudo-op, based on RA/RT=0, and setvli likewise
       sub r3, r3, r4
       ...
     test:
-      setvl. r4, r3, 64
+      setvli. r4, r3, VL=64, MVL=64
       bne cr0, loop
     end:
       blr