* <http://lists.libre-soc.org/pipermail/libre-soc-dev/2020-November/001366.html>
* <https://bugs.libre-soc.org/show_bug.cgi?id=535>
+* <https://bugs.libre-soc.org/show_bug.cgi?id=568> TODO
* <https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#vsetvlivsetvl-instructions>
Use of setvl results in changes to the MVL, VL and STATE SPRs. see [[sv/sprs]]♧
# Format
-| 0.5|6.10|11.15|16.20| 21..24.25 | 26...30 |31| name |
+*(Allocation of opcode TBD pending OPF ISA WG approval)*
+
+| 0.5|6.10|11.15|16.20| 21..24.25 | 26...30 |31| name |
| -- | -- | --- | --- | ----------- | ------- |--| ------- |
| 19 | RT | RA | | XO[0:4] | XO[5:9] |Rc| XL-Form |
| 19 | RT | RA | imm | i // vs ms | NNNNN |Rc| setvl |
Note that imm spans 7 bits (16 to 22), and that bit 22 is reserved and must be zero. Setting bit 22 causes an illegal exception.
-Note that VL and MVL start from **one** i.e. that an immediate value of zero will result in VL/MVL being set to 1. 0b111111 results in VL/MVL being set to 64. This is because setting VL/MVL to 1 results in "scalar identity" behaviour, where setting VL/MVL to 0 would result in all Vector operations becoming nop. If this is truly desired (nop behaviour) then setting VL and MVL to zero be done via the [[SV SPRs|sv/sprs]]
+Note that in immediate setting mode VL and MVL start from **one** i.e. that an immediate value of zero will result in VL/MVL being set to 1. 0b111111 results in VL/MVL being set to 64. This is because setting VL/MVL to 1 results in "scalar identity" behaviour, where setting VL/MVL to 0 would result in all Vector operations becoming `nop`. If this is truly desired (nop behaviour) then setting VL and MVL to zero is to be done via the [[SV SPRs|sv/sprs]]
Note that setmvli is a pseudo-op, based on RA/RT=0, and setvli likewise
sub r3, r3, r4
...
test:
- setvl. r4, r3, 64
+ setvli. r4, r3, VL=64, MVL=64
bne cr0, loop
end:
blr