bug 676: noted a way to reduce the number of instructions

[libreriscv.git] / openpower / sv / setvl.mdwn

diff --git a/openpower/sv/setvl.mdwn b/openpower/sv/setvl.mdwn
index e8bcc44492109c925f22a61b90602da68dae28f7..d2a2031a5b6e3e633ab7c6614d1b1fdd62682a08 100644 (file)
--- a/openpower/sv/setvl.mdwn
+++ b/openpower/sv/setvl.mdwn
@@ -6,9 +6,11 @@ See links:
 * <http://lists.libre-soc.org/pipermail/libre-soc-dev/2020-November/001366.html>
 * <https://bugs.libre-soc.org/show_bug.cgi?id=535>
 * <https://bugs.libre-soc.org/show_bug.cgi?id=587>
+* <https://bugs.libre-soc.org/show_bug.cgi?id=914> TODO: setvl should not set SO
 * <https://bugs.libre-soc.org/show_bug.cgi?id=568> TODO
 * <https://bugs.libre-soc.org/show_bug.cgi?id=927> bug - RT>=32
 * <https://bugs.libre-soc.org/show_bug.cgi?id=862> VF Predication
+* <https://bugs.libre-soc.org/show_bug.cgi?id=1222> Rc=1 enhancement needed
 * <https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#vsetvlivsetvl-instructions>
 * [[sv/svstep]]
 * pseudocode [[openpower/isa/simplev]]