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[libreriscv.git] / openpower / sv / setvl.mdwn

diff --git a/openpower/sv/setvl.mdwn b/openpower/sv/setvl.mdwn
index 59e0e36fb11f6b25456a68e434f424659deb3b1d..e8bcc44492109c925f22a61b90602da68dae28f7 100644 (file)
--- a/openpower/sv/setvl.mdwn
+++ b/openpower/sv/setvl.mdwn
@@ -1,5 +1,6 @@
 # setvl: Set Vector Length
 
+<!-- hide -->
 See links:
 
 * <http://lists.libre-soc.org/pipermail/libre-soc-dev/2020-November/001366.html>
@@ -11,6 +12,7 @@ See links:
 * <https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#vsetvlivsetvl-instructions>
 * [[sv/svstep]]
 * pseudocode [[openpower/isa/simplev]]
+<!-- show -->
 
 Add the following section to the Simple-V Chapter
 
@@ -75,8 +77,8 @@ Note that in immediate setting mode VL and MVL start from **one** but that
 this is compensated for in the assembly notation.  i.e. that an immediate
 value of 1 in assembler notation actually places the value 0b0000000 in
 the `SVi` field bits: on execution the `setvl` instruction adds one to
-the decoded `SVi` field bits, resulting in VL/MVL being set to 1. This
-allows VL to be set to values ranging from 1 to 128 with only 7 bits
+the decoded `SVi` field bits, resulting in VL/MVL being set to 1. In future
+this will allow VL to be set to values ranging from 1 to 128 with only 7 bits
 instead of 8.  Setting VL/MVL to 0 would result in all Vector operations
 becoming `nop`.  If this is truly desired (nop behaviour) then setting
 VL and MVL to zero is to be done via the [[SVSTATE SPR|sv/sprs]].
@@ -118,7 +120,7 @@ from different sources is as follows:
 The reasoning here is that the opportunity to set RT equal to the
 immediate `SVi+1` is sacrificed in favour of setting from CTR.
 
-## Unusual Rc=1 behaviour
+**Unusual Rc=1 behaviour**
 
 Normally, the return result from an instruction is in `RT`. With it
 being possible for `RT=0` to mean that `CTR` mode is to be read, some
@@ -164,7 +166,8 @@ loop:
 ### Loop using Rc=1
 
 In this example, the `setvl.` instruction enabled Rc=1, which
-sets CR0.eq when VL becomes zero.
+sets CR0.eq when VL becomes zero. Testing of `r4` (cmpi) is thus redundant
+saving one instruction.
 
 ```
     my_fn:
@@ -186,14 +189,15 @@ Up to 64 FPRs will be loaded, here.  `r3` is set one per bit for each
 FP register required to be loaded.  The block of memory from which the
 registers are loaded is contiguous (no gaps): any FP register which has
 a corresponding zero bit in `r3` is *unaltered*.  In essence this is a
-selective LD-multi with "Scatter" capability.
+selective LD-multi with "Scatter" (`VCOMPRESS`) capability.
 
 ```
     setvli r0, MVL=64, VL=64
     sv.fld/dm=r3 *r0, 0(r30) # selective load 64 FP registers
 ```
 
-Up to 64 FPRs will be saved, here.  Again, `r3` 
+Up to 64 FPRs will be saved, here.  Again, `r3` specifies which
+registers are set in a `VEXPAND` fashion.
 
 ```
     setvli r0, MVL=64, VL=64