| **SVSTATE** | 64-bit | Zero-Overhead Loop Architectural State |
| **SVLR** | 64-bit | SVSTATE equivalent of LR-to-PC |
| **SVSHAPE0** | 32-bit | REMAP Shape 0 |
-| **SVSHAPE1** | 32-bit | REMAP Shape 0 |
-| **SVSHAPE2** | 32-bit | REMAP Shape 0 |
-| **SVSHAPE3** | 32-bit | REMAP Shape 0 |
+| **SVSHAPE1** | 32-bit | REMAP Shape 1 |
+| **SVSHAPE2** | 32-bit | REMAP Shape 2 |
+| **SVSHAPE3** | 32-bit | REMAP Shape 3 |
Future versions of Simple-V will have at least 7 more SVSTATE SPRs, in a small
"stack", as part of a full Zero-Overhead Loop Control subsystem.
so Scalar instructions (except the SVP64 Management ones and mtspr and
mfspr) are 100% guaranteed to have zero impact on SVP64 state.
+**SVme REMAP area**
+
+Each bit of `SVSTATE.SVme` indicates whether the SVSHAPE (0-3) is active and to which register
+the REMAP applies. The application goes by *assembler operand names* on a per-mnemonic
+basis. Some instructions may have `RT` as a source and as a destination: REMAP applies
+**separately** to each use in this case. Also for Load/Store with Update the Effective
+Address (stored in EA) also may be separately REMAPed from RA as a source operand.
+
+| bit|applies|register applied|
+|----|-------|----------------|
+| 46 | mi0 | source RA / FRA / BA / BFA / RT / FRT |
+| 45 | mi1 | source RB / FRB / BB|
+| 44 | mi2 | source RC / FRC / BC|
+| 43 | mo0 | result RT / FRT / BT / BF|
+| 42 | mo1 | result Effective Address (RA) / FRS / RS|
+
**Max Vector Length (maxvl)** <a name="mvl" />
MAXVECTORLENGTH is a static (immediate-operand only) compile-time declaration