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[libreriscv.git] / openpower / sv / sprs.mdwn

diff --git a/openpower/sv/sprs.mdwn b/openpower/sv/sprs.mdwn
index 5bfe566fda86ea745db772e532b6869d991dae49..284ee61c3c7122d69cc7295c7425a559b8c791b4 100644 (file)
--- a/openpower/sv/sprs.mdwn
+++ b/openpower/sv/sprs.mdwn
@@ -2,12 +2,20 @@
 
 # SPRs <a name="sprs"></a>
 
+Note OpenPOWER v3.1B p12:
+
+     The designated SPR sandbox consists of non-privileged SPRs
+     704-719 and privileged SPRs 720-735.
+
 There are five SPRs, available in any privilege level:
 
 * MVL (the Maximum Vector Length)
 * VL (which has different characteristics from standard SPRs)
 * SUBVL (effectively a kind of SIMD)
 * STATE (containing copies of MVL, VL and SUBVL as well as context information)
+* SVSRR0 which is used for exceptions and traps to store SVSTATE.
+
+MVL, VL and SUBVL are only provided for convenience: normally [[sv/setvl]] would be used to obtain a copy of VL, for example.
 
 For Privilege Levels (trap handling) there are the following SPRs,
 where x may be u, s or h for User, Supervisor or Hypervisor
@@ -20,13 +28,13 @@ The u/s SPRs are treated and handled exactly like their (x)epc
 equivalents.  On entry to or exit from a privilege level, the contents
 of its (x)eSTATE are swapped with STATE.
 
-## MAXVECTORLENGTH (MVL) <a name="mvl" />
+# MAXVECTORLENGTH (MVL) <a name="mvl" />
 
 MAXVECTORLENGTH is the same concept as MVL in RVV, except that it
 is variable length and may be dynamically set.  MVL is
 however limited to the regfile bitwidth, 64.
 
-## Vector Length (VL) <a name="vl" />
+# Vector Length (VL) <a name="vl" />
 
 VSETVL is slightly different from RVV.  Similar to RVV, VL is set to be within
 the range 0 <= VL <= MVL (where MVL in turn is limited to 1 <= MVL <= XLEN)
@@ -35,7 +43,7 @@ the range 0 <= VL <= MVL (where MVL in turn is limited to 1 <= MVL <= XLEN)
 
 where 1 <= MVL <= XLEN
 
-## SUBVL - Sub Vector Length
+# SUBVL - Sub Vector Length
 
 This is a "group by quantity" that effectively asks each iteration
 of the hardware loop to load SUBVL elements of width elwidth at a
@@ -46,10 +54,10 @@ The main effect of SUBVL is that predication bits are applied per
 **group**, rather than by individual element.  Legal values are 1 to 4.
 Illegal values raise an exception.
 
-## STATE
+# STATE
 
 This is a standard SPR that contains sufficient information for a
-full context save/restore.  It contains (and permits setting of):
+full context save/restore (see SVSRR0).  It contains (and permits setting of):
 
 * MVL
 * VL
@@ -64,16 +72,16 @@ The format of the STATE SPR is as follows:
 
 | Field | Name     | Description           |
 | ----- | -------- | --------------------- |
-| 0:6   | maxvl    | Max Vector Length |
-| 7:13  |    vl    | Vector Length |
-| 14:20 | srcstep  | |
-| 21:27 | dststep  | |
-| 28:29 | subvl    | |
-| 30:31 | svstep   | |
+| 0:6   | maxvl    | Max Vector Length     |
+| 7:13  |    vl    | Vector Length         |
+| 14:20 | srcstep  | for srcstep = 0..VL-1 |
+| 21:27 | dststep  | for dststep = 0..VL-1 |
+| 28:29 | subvl    | Sub-vector length     |
+| 30:31 | svstep   | for svstep = 0..SUBVL-1  |
 
 The relationship between SUBVL and the subvl field is:
 
-| SUBVL | (25..24) |
+| SUBVL | (29..28) |
 | ----- | -------- |
 | 1     | 0b00     |
 | 2     | 0b01     |
@@ -87,3 +95,17 @@ Notes:
 * Setting srcstep, dststep to 64 or greater, or VL or MVL to greater
   than 64 is reserved and will cause an illegal instruction trap.
 
+# SVSRR0
+
+In scalar v3.0B traps, exceptions and interrupts, two SRRs are saved/restored:
+
+* SRR0 to store the PC (CIA/NIA)
+* SRR1 to store a copy of the MSR
+
+Given that SVSTATE is effectively a Sub-PC it is critically important to add saving/restoring of SVSTATE as a full peer equal in status to PC, in every way.  At any time PC is saved or restored, so is SVSTATE in **exactly** the same way for **exactly** the same reasons.
+
+The SPR name given for the purposes of saving/restoring SVSTATE is SVSRR0.
+
+
+
+