# SPRs <a name="sprs"></a>
-Note OpenPOWER v3.1B p12:
+Note OpenPOWER v3.1 p12:
The designated SPR sandbox consists of non-privileged SPRs
704-719 and privileged SPRs 720-735.
There are five SPRs, available in any privilege level:
-* MVL (the Maximum Vector Length)
-* VL (which has different characteristics from standard SPRs)
-* SUBVL (effectively a kind of SIMD)
* SVSTATE (containing copies of MVL, VL and SUBVL as well as context information)
* SVSRR0 which is used for exceptions and traps to store SVSTATE.
-
-MVL, VL and SUBVL are only provided for convenience: normally [[sv/setvl]] would be used to obtain a copy of VL, for example.
+* SVLR, a mirror of LR, used by Vectorised Branch
+* SVSHAPE0-3 for REMAP purposes, re-shaping Vector loops
+* SVREMAP for applying specific shapes to specific registers
For Privilege Levels (trap handling) there are the following SPRs,
where x may be u, s or h for User, Supervisor or Hypervisor
equivalents. On entry to or exit from a privilege level, the contents
of its (x)eSTATE are swapped with SVSTATE.
-# MAXVECTORLENGTH (MVL) <a name="mvl" />
-
-MAXVECTORLENGTH is the same concept as MVL in RVV, except that it
-is variable length and may be dynamically set. MVL is
-however limited to the regfile bitwidth, 64.
-
-# Vector Length (VL) <a name="vl" />
-
-VSETVL is slightly different from RVV. Similar to RVV, VL is set to be within
-the range 0 <= VL <= MVL (where MVL in turn is limited to 1 <= MVL <= XLEN)
-
- VL = rd = MIN(vlen, MVL)
-
-where 1 <= MVL <= XLEN
-
-# SUBVL - Sub Vector Length
-
-This is a "group by quantity" that effectively asks each iteration
-of the hardware loop to load SUBVL elements of width elwidth at a
-time. Effectively, SUBVL is like a SIMD multiplier: instead of just 1
-operation issued, SUBVL operations are issued.
-
-The main effect of SUBVL is that predication bits are applied per
-**group**, rather than by individual element. Legal values are 1 to 4.
-Illegal values raise an exception.
-
# SVSTATE
This is a standard SPR that contains sufficient information for a
full context save/restore (see SVSRR0). It contains (and permits setting of):
-* MVL
-* VL
+* MVL (the Maximum Vector Length) - declares (statically) how
+ much of a regfile is to be reserved for Vector elements
+* VL - Vector Length
* dststep - the destination element offset of the current parallel
instruction being executed
* srcstep - for twin-predication, the source element offset as well.
* vfirst - Vertical First mode. srcstep, dststep and substep
**do not advance** unless explicitly requested to do so with
pseudo-op svstep (a mode of setvl)
+* RMpst - REMAP persistence. REMAP will apply only to the following
+ instruction unless this bit is set, in which case REMAP "persists".
+ Reset (cleared) on use of the `setvl` instruction if used to
+ alter VL or MVL.
* hphint - Horizontal Parallelism Hint. In Vertical First Mode
hardware **MAY** perform up to this many elements in parallel
per instruction. Set to zero to indicate "no hint".
indicate the SVSHAPE (0-3) that the corresponding register (RA etc)
should use.
+**MAXVECTORLENGTH (MVL)** <a name="mvl" />
+
+MAXVECTORLENGTH is the same concept as MVL in RVV, except that it
+is variable length and may be dynamically set. MVL is
+however limited to the regfile bitwidth, 64.
+
+**Vector Length (VL)** <a name="vl" />
+
+VSETVL is slightly different from RVV. Similar to RVV, VL is set to be within
+the range 0 <= VL <= MVL (where MVL in turn is limited to 1 <= MVL <= XLEN)
+
+ VL = rd = MIN(vlen, MVL)
+
+where 1 <= MVL <= XLEN
+
+**SUBVL - Sub Vector Length**
+
+This is a "group by quantity" that effectively asks each iteration
+of the hardware loop to load SUBVL elements of width elwidth at a
+time. Effectively, SUBVL is like a SIMD multiplier: instead of just 1
+operation issued, SUBVL operations are issued.
+
+The main effect of SUBVL is that predication bits are applied per
+**group**, rather than by individual element. Legal values are 1 to 4.
+Illegal values raise an exception.
+
For hphint, the number chosen must be consistently
executed **every time**. Hardware is not permitted to execute five
computations for one instruction then three on the next.
| 38:39 | mo0 | REMAP RT SVSHAPE0-3 |
| 40:41 | mo1 | REMAP EA SVSHAPE0-3 |
| 42:46 | SVme | REMAP enable (RA-RT) |
-| 47:54 | rsvd | reserved |
-| 55:61 | hphint | horizontal parallelism hint |
+| 47:48 | srcsubvl | Source Sub-vector length |
+| 49:61 | rsvd | reserved |
| 62 | RMpst | REMAP persistence |
| 63 | vfirst | Vertical First mode |
The SPR name given for the purposes of saving/restoring
SVSTATE is SVSRR0.
+
+# SVLR
+
+SV Link Register, exactly analogous to LR (Link Register) may
+be used for temporary storage of SVSTATE, and, in particular,
+Vectorised Branch-Conditional instructions may interchange
+SVLR and SVSTATE whenever LR and NIA are.
+
+Note that there is no equivalent Link variant of SVREMAP or
+SVSHAPE0-3, so SVLR has limited applicability
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