# SPRs <a name="sprs"></a>
-Note OpenPOWER v3.1B p12:
+Note OpenPOWER v3.1 p12:
The designated SPR sandbox consists of non-privileged SPRs
704-719 and privileged SPRs 720-735.
* MVL (the Maximum Vector Length)
* VL (which has different characteristics from standard SPRs)
-* SUBVL (effectively a kind of SIMD)
+* SUBVL (effectively a kind of Packed SIMD of size 2, 3 or 4)
* SVSTATE (containing copies of MVL, VL and SUBVL as well as context information)
* SVSRR0 which is used for exceptions and traps to store SVSTATE.
* vfirst - Vertical First mode. srcstep, dststep and substep
**do not advance** unless explicitly requested to do so with
pseudo-op svstep (a mode of setvl)
+* RMpst - REMAP persistence. REMAP will apply only to the following
+ instruction unless this bit is set, in which case REMAP "persists".
+ Reset (cleared) on use of the `setvl` instruction if used to
+ alter VL or MVL.
* hphint - Horizontal Parallelism Hint. In Vertical First Mode
hardware **MAY** perform up to this many elements in parallel
per instruction. Set to zero to indicate "no hint".
| 38:39 | mo0 | REMAP RT SVSHAPE0-3 |
| 40:41 | mo1 | REMAP EA SVSHAPE0-3 |
| 42:46 | SVme | REMAP enable (RA-RT) |
-| 47:54 | rsvd | reserved |
-| 55:61 | hphint | horizontal parallelism hint |
+| 47:48 | srcsubvl | Source Sub-vector length |
+| 49:61 | rsvd | reserved |
| 62 | RMpst | REMAP persistence |
| 63 | vfirst | Vertical First mode |