(no commit message)

[libreriscv.git] / openpower / sv / sprs.mdwn

diff --git a/openpower/sv/sprs.mdwn b/openpower/sv/sprs.mdwn
index 002eede7e381fc235244e7eb22664198408195d7..ac4d2fa51d37dc7c7c85b46ead7edb5a770f7424 100644 (file)
--- a/openpower/sv/sprs.mdwn
+++ b/openpower/sv/sprs.mdwn
@@ -73,6 +73,11 @@ full context save/restore (see SVSRR0).  It contains (and permits setting of):
 * hphint - Horizontal Parallelism Hint. In Vertical First Mode
    hardware **MAY** perform up to this many elements in parallel
    per instruction. Set to zero to indicate "no hint".
+* SVme - REMAP enable bits, indicating which register is to be
+ REMAPed.  RA, RB, RC, RT or EA.
+* mi0-mi4 - when the corresponding SVme bit is enabled, mi0-mi4
+  indicate the SVSHAPE (0-3) that the corresponding register (RA etc)
+  should use.
 
 For hphint, the number chosen must be consistently
 executed **every time**. Hardware is not permitted to execute five
@@ -137,4 +142,5 @@ Given that SVSTATE is effectively a Sub-PC it is critically important to add sav
 hardware **must** save/restore SVSTATE in SVSRR0 at exactly the same
 time that SRR0 is saved/restored in PC and SRR1 in MSR.
 
-The SPR name given for the purposes of saving/restoring SVSTATE is SVSRR0.
+The SPR name given for the purposes of saving/restoring
+SVSTATE is SVSRR0.