(no commit message)

[libreriscv.git] / openpower / sv / sprs.mdwn

diff --git a/openpower/sv/sprs.mdwn b/openpower/sv/sprs.mdwn
index 957bebbf1dbe5c43dda65cb250e32d310c9d68e6..d5ebd7d93881741365c7dd4f6bd06a6cd7429b01 100644 (file)
--- a/openpower/sv/sprs.mdwn
+++ b/openpower/sv/sprs.mdwn
@@ -6,24 +6,18 @@ There are five CSRs, available in any privilege level:
 * VL (which has different characteristics from standard CSRs)
 * SUBVL (effectively a kind of SIMD)
 * STATE (containing copies of MVL, VL and SUBVL as well as context information)
-* PCVBLK (the current operation being executed within a VBLOCK Group)
 
 For Privilege Levels (trap handling) there are the following CSRs,
-where x may be u, m, s or h for User, Machine, Supervisor or Hypervisor
+where x may be u, s or h for User, Supervisor or Hypervisor
 Modes respectively:
 
-* (x)ePCVBLK (a copy of the sub-execution Program Counter, that is relative
-  to the start of the current VBLOCK Group, set on a trap).
 * (x)eSTATE (useful for saving and restoring during context switch,
   and for providing fast transitions)
 
-The u/m/s CSRs are treated and handled exactly like their (x)epc
+The u/s CSRs are treated and handled exactly like their (x)epc
 equivalents.  On entry to or exit from a privilege level, the contents
 of its (x)eSTATE are swapped with STATE.
 
-(x)EPCVBLK CSRs must be treated exactly like their corresponding (x)epc
-equivalents. See VBLOCK section for details.
-
 ## MAXVECTORLENGTH (MVL) <a name="mvl" />
 
 MAXVECTORLENGTH is the same concept as MVL in RVV, except that it
@@ -58,18 +52,23 @@ full context save/restore.  It contains (and permits setting of):
 
 * MVL
 * VL
-* destoffs - the destination element offset of the current parallel
+* dsttoffs - the destination element offset of the current parallel
   instruction being executed
 * srcoffs - for twin-predication, the source element offset as well.
 * SUBVL
-* dsvoffs - the subvector destination element offset of the current
+* svoffs - the subvector element offset of the current
   parallel instruction being executed
 
 The format of the STATE CSR is as follows:
 
-| (31..28) | (27..26) | (25..24) | (23..18) | (17..12) | (11..6) | (5...0) |
-| -------- | -------- | -------- | -------- | -------- | ------- | ------- |
-| rsvd     | dsvoffs  | subvl    | destoffs | srcoffs  | vl      | maxvl   |
+| Field | Name     | Description           |
+| ----- | -------- | --------------------- |
+| 0:6   | maxvl    | Max Vector Length |
+| 7:13  |    vl    | Vector Length |
+| 14:20 | srcoffs  | |
+| 21:27 | dstoffs  | |
+| 28:29 | subvl    | |
+| 30:31 | svoffs   | |
 
 The relationship between SUBVL and the subvl field is:
 
@@ -84,6 +83,5 @@ Notes:
 
 * The entries are truncated to be within range.  Attempts to set VL to
   greater than MAXVL will truncate VL.
-* Both VL and MAXVL are stored offset by one.  0b000000 represents VL=1,
-  0b000001 represents VL=2.  This allows the full range 1 to XLEN instead
-  of 0 to only 63.
+* Setting srcoffs, dstoffs to 64 or greater, or VL or MVL to greater than 64 is reserved and will cause an illegal instruction trap.
+