* <https://bugs.libre-soc.org/show_bug.cgi?id=574>
* <https://bugs.libre-soc.org/show_bug.cgi?id=558#c47>
+* <https://bugs.libre-soc.org/show_bug.cgi?id=697>
This is the appendix to [[sv/svp64]], providing explanations of modes
-etc. leaving the main svp64 page's primary purpose as outlining the instruction format.
+etc. leaving the main svp64 page's primary purpose as outlining the
+instruction format.
Table of contents:
Read-Write Hazards on single-bit global resources, having a significant
detrimental effect.
-Consequently in SV, XER.SO and CR.OV behaviour is disregarded (including in `cmp` instructions). XER is
-simply neither read nor written. This includes when `scalar identity behaviour` occurs. If precise OpenPOWER v3.0/1 scalar behaviour is desired then OpenPOWER v3.0/1 instructions should be used without an SV Prefix.
-
-An interesting side-effect of this decision is that the OE flag is now free for other uses when SV Prefixing is used.
-
-Regarding XER.CA: this does not fit either: it was designed for a scalar ISA. Instead, both carry-in and carry-out go into the CR.so bit of a given Vector element. This provides a means to perform large parallel batches of Vectorised carry-capable additions. crweird instructions can be used to transfer the CRs in and out of an integer, where bitmanipulation may be performed to analyse the carry bits (including carry lookahead propagation) before continuing with further parallel additions.
-
-# v3.0B/v3.1B relevant instructions
-
-SV is primarily designed for use as an efficient hybrid 3D GPU / VPU / CPU ISA.
-
-As mentioned above, OE=1 is not applicable in SV, freeing this bit for alternative uses. Additionally, Vectorisation of the VSX SIMD system likewise makes no sense whatsoever. SV *replaces* VSX and provides, at the very minimum, predication (which VSX was designed without). Thus all VSX Major Opcodes - all of them - are "unused" and must raise illegal instruction exceptions in SV Prefix Mode.
-
-Likewise, `lq` (Load Quad), and Load/Store Multiple make no sense to have because they are not only provided by SV, the SV alternatives may be predicated as well, making them far better suited to use in function calls and context-switching.
-
-Additionally, some v3.0/1 instructions simply make no sense at all in a Vector context: `twi` and `tdi` fall into this category, as do branch operations as well as `sc` and `scv`. Here there is simply no point trying to Vectorise them: the standard OpenPOWER v3.0/1 instructions should be called instead.
-
-Fortuitously this leaves several Major Opcodes free for use by SV to fit alternative future instructions. In a 3D context this means Vector Product, Vector Normalise, [[sv/mv.swizzle]], Texture LD/ST operations, and others critical to an efficient, effective 3D GPU and VPU ISA. With such instructions being included as standard in other commercially-successful GPU ISAs it is likewise critical that a 3D GPU/VPU based on svp64 also have such instructions.
-
-Note however that svp64 is stand-alone and is in no way critically dependent on the existence or provision of 3D GPU or VPU instructions. These should be considered extensions, and their discussion and specification is out of scope for this document.
-
-Note, again: this is *only* under svp64 prefixing. Standard v3.0B / v3.1B is *not* altered by svp64 in any way.
+Consequently in SV, XER.SO and CR.OV behaviour is disregarded (including
+in `cmp` instructions). XER is simply neither read nor written.
+This includes when `scalar identity behaviour` occurs. If precise
+OpenPOWER v3.0/1 scalar behaviour is desired then OpenPOWER v3.0/1
+instructions should be used without an SV Prefix.
+
+An interesting side-effect of this decision is that the OE flag is now
+free for other uses when SV Prefixing is used.
+
+Regarding XER.CA: this does not fit either: it was designed for a scalar
+ISA. Instead, both carry-in and carry-out go into the CR.so bit of a given
+Vector element. This provides a means to perform large parallel batches
+of Vectorised carry-capable additions. crweird instructions can be used
+to transfer the CRs in and out of an integer, where bitmanipulation
+may be performed to analyse the carry bits (including carry lookahead
+propagation) before continuing with further parallel additions.
+
+# v3.0B/v3.1 relevant instructions
+
+SV is primarily designed for use as an efficient hybrid 3D GPU / VPU /
+CPU ISA.
+
+As mentioned above, OE=1 is not applicable in SV, freeing this bit for
+alternative uses. Additionally, Vectorisation of the VSX SIMD system
+likewise makes no sense whatsoever. SV *replaces* VSX and provides,
+at the very minimum, predication (which VSX was designed without).
+Thus all VSX Major Opcodes - all of them - are "unused" and must raise
+illegal instruction exceptions in SV Prefix Mode.
+
+Likewise, `lq` (Load Quad), and Load/Store Multiple make no sense to
+have because they are not only provided by SV, the SV alternatives may
+be predicated as well, making them far better suited to use in function
+calls and context-switching.
+
+Additionally, some v3.0/1 instructions simply make no sense at all in a
+Vector context: `rfid` falls into this category,
+as well as `sc` and `scv`. Here there is simply no point
+trying to Vectorise them: the standard OpenPOWER v3.0/1 instructions
+should be called instead.
+
+Fortuitously this leaves several Major Opcodes free for use by SV
+to fit alternative future instructions. In a 3D context this means
+Vector Product, Vector Normalise, [[sv/mv.swizzle]], Texture LD/ST
+operations, and others critical to an efficient, effective 3D GPU and
+VPU ISA. With such instructions being included as standard in other
+commercially-successful GPU ISAs it is likewise critical that a 3D
+GPU/VPU based on svp64 also have such instructions.
+
+Note however that svp64 is stand-alone and is in no way
+critically dependent on the existence or provision of 3D GPU or VPU
+instructions. These should be considered extensions, and their discussion
+and specification is out of scope for this document.
+
+Note, again: this is *only* under svp64 prefixing. Standard v3.0B /
+v3.1B is *not* altered by svp64 in any way.
## Major opcode map (v3.0B)
111 | lq | EXT57 | EXT58 | EXT59 | EXT60 | EXT61 | EXT62 | EXT63 | 111
| 000 | 001 | 010 | 011 | 100 | 101 | 110 | 111
-## Suitable for svp64
+## Suitable for svp64-only
-This is the same table containing v3.0B Primary Opcodes except those that make no sense in a Vectorisation Context have been removed. These removed POs can, *in the SV Vector Context only*, be assigned to alternative (Vectorised-only) instructions, including future extensions.
+This is the same table containing v3.0B Primary Opcodes except those that
+make no sense in a Vectorisation Context have been removed. These removed
+POs can, *in the SV Vector Context only*, be assigned to alternative
+(Vectorised-only) instructions, including future extensions.
-Note, again, to emphasise: outside of svp64 these opcodes **do not** change. When not prefixed with svp64 these opcodes **specifically** retain their v3.0B / v3.1B OpenPOWER Standard compliant meaning.
+Note, again, to emphasise: outside of svp64 these opcodes **do not**
+change. When not prefixed with svp64 these opcodes **specifically**
+retain their v3.0B / v3.1B OpenPOWER Standard compliant meaning.
| 000 | 001 | 010 | 011 | 100 | 101 | 110 | 111
000 | | | | | | | | mulli | 000
111 | | | EXT58 | EXT59 | | EXT61 | | EXT63 | 111
| 000 | 001 | 010 | 011 | 100 | 101 | 110 | 111
+It is important to note that having a different v3.0B Scalar opcode
+that is different from an SVP64 one is highly undesirable: the complexity
+in the decoder is greatly increased.
+
+# Single Predication
+
+This is a standard mode normally found in Vector ISAs. every element in every source Vector and in the destination uses the same bit of one single predicate mask.
+
+In SVSTATE, for Single-predication, implementors MUST increment both srcstep and dststep: unlike Twin-Predication the two must be equal at all times.
+
# Twin Predication
This is a novel concept that allows predication to be applied to a single
particularly given that one of the predicate options is `(1<<r3)`
Additional unusual capabilities of Twin Predication include a back-to-back
-version of VCOMPRESS-VEXPAND which is effectively the ability to do
-sequentially ordered multiple VINSERTs. The source predicate selects a
-sequentially ordered subset of elements to be inserted; the destination predicate specifies the sequentially ordered recipient locations.
+version of VCOMPRESS-VEXPAND which is effectively the ability to do
+sequentially ordered multiple VINSERTs. The source predicate selects a
+sequentially ordered subset of elements to be inserted; the destination
+predicate specifies the sequentially ordered recipient locations.
This is equivalent to
`llvm.masked.compressstore.*`
followed by
`llvm.masked.expandload.*`
-
-# Rounding, clamp and saturate
-
-see [[av_opcodes]].
-
-To help ensure that audio quality is not compromised by overflow,
-"saturation" is provided, as well as a way to detect when saturation
-occurred if desired (Rc=1). When Rc=1 there will be a *vector* of CRs, one CR per
-element in the result (Note: this is different from VSX which has a
-single CR per block).
-
-When N=0 the result is saturated to within the maximum range of an
-unsigned value. For integer ops this will be 0 to 2^elwidth-1. Similar
-logic applies to FP operations, with the result being saturated to
-maximum rather than returning INF, and the minimum to +0.0
-
-When N=1 the same occurs except that the result is saturated to the min
-or max of a signed result, and for FP to the min and max value rather than returning +/- INF.
-
-When Rc=1, the CR "overflow" bit is set on the CR associated with the
-element, to indicate whether saturation occurred. Note that due to
-the hugely detrimental effect it has on parallel processing, XER.SO is
-**ignored** completely and is **not** brought into play here. The CR
-overflow bit is therefore simply set to zero if saturation did not occur,
-and to one if it did.
-
-Note also that saturate on operations that produce a carry output are prohibited due to the conflicting use of the CR.so bit for storing if saturation occurred.
-
-Post-analysis of the Vector of CRs to find out if any given element hit
-saturation may be done using a mapreduced CR op (cror), or by using the
-new crweird instruction, transferring the relevant CR bits to a scalar
-integer and testing it for nonzero. see [[sv/cr_int_predication]]
-
-Note that the operation takes place at the maximum bitwidth (max of src and dest elwidth) and that truncation occurs to the range of the dest elwidth.
-
-# Reduce mode
-
-1. limited to single predicated dual src operations (add RT, RA, RB).
- triple source operations are prohibited (fma).
-2. limited to operations that make sense. divide is excluded, as is
- subtract (X - Y - Z produces different answers depending on the order)
- and asymmetric CRops (crandc, crorc). sane operations:
- multiply, min/max, add, logical bitwise OR, most other CR ops.
- operations that do have the same source and dest register type are
- also excluded (isel, cmp). operations involving carry or overflow
- (XER.CA / OV) are also prohibited.
-3. the destination is a vector but the result is stored, ultimately,
- in the first nonzero predicated element. all other nonzero predicated
- elements are undefined. *this includes the CR vector* when Rc=1
-4. implementations may use any ordering and any algorithm to reduce
- down to a single result. However it must be equivalent to a straight
- application of mapreduce. The destination vector (except masked out
- elements) may be used for storing any intermediate results. these may
- be left in the vector (undefined).
-5. CRM applies when Rc=1. When CRM is zero, the CR associated with
- the result is regarded as a "some results met standard CR result
- criteria". When CRM is one, this changes to "all results met standard
- CR criteria".
-6. implementations MAY use destoffs as well as srcoffs (see [[sv/sprs]])
- in order to store sufficient state to resume operation should an
- interrupt occur. this is also why implementations are permitted to use
- the destination vector to store intermediary computations
-7. *Predication may be applied*. zeroing mode is not an option. masked-out
- inputs are ignored; masked-out elements in the destination vector are
- unaltered (not used for the purposes of intermediary storage); the
- scalar result is placed in the first available unmasked element.
-
-Pseudocode for the case where RA==RB:
-
- result = op(iregs[RA], iregs[RA+1])
- CR = analyse(result)
- for i in range(2, VL):
- result = op(result, iregs[RA+i])
- CRnew = analyse(result)
- if Rc=1
- if CRM:
- CR = CR bitwise or CRnew
- else:
- CR = CR bitwise AND CRnew
-
-TODO: case where RA!=RB which involves first a vector of 2-operand
-results followed by a mapreduce on the intermediates.
-
-Note that when SVM is clear and SUBVL!=1 the sub-elements are *independent*, i.e. they
-are mapreduced per *sub-element* as a result. illustration with a vec2:
-
- result.x = op(iregs[RA].x, iregs[RA+1].x)
- result.y = op(iregs[RA].y, iregs[RA+1].y)
- for i in range(2, VL):
- result.x = op(result.x, iregs[RA+i].x)
- result.y = op(result.y, iregs[RA+i].y)
-
-Note here that Rc=1 does not make sense when SVM is clear and SUBVL!=1.
-
-When SVM is set and SUBVL!=1, another variant is enabled: horizontal subvector mode. Example for a vec3:
+# Reduce modes
+
+Reduction in SVP64 is deterministic and somewhat of a misnomer. A normal
+Vector ISA would have explicit Reduce opcodes with defined characteristics
+per operation: in SX Aurora there is even an additional scalar argument
+containing the initial reduction value, and the default is either 0
+or 1 depending on the specifics of the explicit opcode.
+SVP64 fundamentally has to
+utilise *existing* Scalar Power ISA v3.0B operations, which presents some
+unique challenges.
+
+The solution turns out to be to simply define reduction as permitting
+deterministic element-based schedules to be issued using the base Scalar
+operations, and to rely on the underlying microarchitecture to resolve
+Register Hazards at the element level. This goes back to
+the fundamental principle that SV is nothing more than a Sub-Program-Counter
+sitting between Decode and Issue phases.
+
+Microarchitectures *may* take opportunities to parallelise the reduction
+but only if in doing so they preserve Program Order at the Element Level.
+Opportunities where this is possible include an `OR` operation
+or a MIN/MAX operation: it may be possible to parallelise the reduction,
+but for Floating Point it is not permitted due to different results
+being obtained if the reduction is not executed in strict sequential
+order.
+
+In essence it becomes the programmer's responsibility to leverage the
+pre-determined schedules to desired effect.
+
+## Scalar result reduction and iteration
+
+Scalar Reduction per se does not exist, instead is implemented in SVP64
+as a simple and natural relaxation of the usual restriction on the Vector
+Looping which would terminate if the destination was marked as a Scalar.
+Scalar Reduction by contrast *keeps issuing Vector Element Operations*
+even though the destination register is marked as scalar.
+Thus it is up to the programmer to be aware of this and observe some
+conventions.
+
+It is also important to appreciate that there is no
+actual imposition or restriction on how this mode is utilised: there
+will therefore be several valuable uses (including Vector Iteration
+and "Reverse-Gear")
+and it is up to the programmer to make best use of the
+(strictly deterministic) capability
+provided.
+
+In this mode, which is suited to operations involving carry or overflow,
+one register must be assigned, by convention by the programmer to be the
+"accumulator". Scalar reduction is thus categorised by:
+
+* One of the sources is a Vector
+* the destination is a scalar
+* optionally but most usefully when one source scalar register is
+ also the scalar destination (which may be informally termed
+ the "accumulator")
+* That the source register type is the same as the destination register
+ type identified as the "accumulator". Scalar reduction on `cmp`,
+ `setb` or `isel` makes no sense for example because of the mixture
+ between CRs and GPRs.
+
+*Note that issuing instructions in Scalar reduce mode such as `setb`
+are neither `UNDEFINED` nor prohibited, despite them not making much
+sense at first glance.
+Scalar reduce is strictly defined behaviour, and the cost in
+hardware terms of prohibition of seemingly non-sensical operations is too great.
+Therefore it is permitted and required to be executed successfully.
+Implementors **MAY** choose to optimise such instructions in instances
+where their use results in "extraneous execution", i.e. where it is clear
+that the sequence of operations, comprising multiple overwrites to
+a scalar destination **without** cumulative, iterative, or reductive
+behaviour (no "accumulator"), may discard all but the last element
+operation. Identification
+of such is trivial to do for `setb` and `cmp`: the source register type is
+a completely different register file from the destination*
+
+Typical applications include simple operations such as `ADD r3, r10.v,
+r3` where, clearly, r3 is being used to accumulate the addition of all
+elements is the vector starting at r10.
+
+ # add RT, RA,RB but when RT==RA
+ for i in range(VL):
+ iregs[RA] += iregs[RB+i] # RT==RA
+
+However, *unless* the operation is marked as "mapreduce" (`sv.add/mr`)
+SV ordinarily
+**terminates** at the first scalar operation. Only by marking the
+operation as "mapreduce" will it continue to issue multiple sub-looped
+(element) instructions in `Program Order`.
+
+To perform the loop in reverse order, the ```RG``` (reverse gear) bit must be set. This may be useful in situations where the results may be different
+(floating-point) if executed in a different order. Given that there is
+no actual prohibition on Reduce Mode being applied when the destination
+is a Vector, the "Reverse Gear" bit turns out to be a way to apply Iterative
+or Cumulative Vector operations in reverse. `sv.add/rg r3.v, r4.v, r4.v`
+for example will start at the opposite end of the Vector and push
+a cumulative series of overlapping add operations into the Execution units of
+the underlying hardware.
+
+Other examples include shift-mask operations where a Vector of inserts
+into a single destination register is required, as a way to construct
+a value quickly from multiple arbitrary bit-ranges and bit-offsets.
+Using the same register as both the source and destination, with Vectors
+of different offsets masks and values to be inserted has multiple
+applications including Video, cryptography and JIT compilation.
+
+Subtract and Divide are still permitted to be executed in this mode,
+although from an algorithmic perspective it is strongly discouraged.
+It would be better to use addition followed by one final subtract,
+or in the case of divide, to get better accuracy, to perform a multiply
+cascade followed by a final divide.
+
+Note that single-operand or three-operand scalar-dest reduce is perfectly
+well permitted: the programmer may still declare one register, used as
+both a Vector source and Scalar destination, to be utilised as
+the "accumulator". In the case of `sv.fmadds` and `sv.maddhw` etc
+this naturally fits well with the normal expected usage of these
+operations.
+
+If an interrupt or exception occurs in the middle of the scalar mapreduce,
+the scalar destination register **MUST** be updated with the current
+(intermediate) result, because this is how ```Program Order``` is
+preserved (Vector Loops are to be considered to be just another way of issuing instructions
+in Program Order). In this way, after return from interrupt,
+the scalar mapreduce may continue where it left off. This provides
+"precise" exception behaviour.
+
+Note that hardware is perfectly permitted to perform multi-issue
+parallel optimisation of the scalar reduce operation: it's just that
+as far as the user is concerned, all exceptions and interrupts **MUST**
+be precise.
+
+## Vector result reduce mode
+
+Vector Reduce Mode issues a deterministic tree-reduction schedule to the underlying micro-architecture. Like Scalar reduction, the "Scalar Base"
+(Power ISA v3.0B) operation is leveraged, unmodified, to give the
+*appearance* and *effect* of Reduction.
+
+Given that the tree-reduction schedule is deterministic,
+Interrupts and exceptions
+can therefore also be precise. The final result will be in the first
+non-predicate-masked-out destination element, but due again to
+the deterministic schedule programmers may find uses for the intermediate
+results.
+
+When Rc=1 a corresponding Vector of co-resultant CRs is also
+created. No special action is taken: the result and its CR Field
+are stored "as usual" exactly as all other SVP64 Rc=1 operations.
+
+## Sub-Vector Horizontal Reduction
+
+Note that when SVM is clear and SUBVL!=1 the sub-elements are
+*independent*, i.e. they are mapreduced per *sub-element* as a result.
+illustration with a vec2, assuming RA==RT, e.g `sv.add/mr/vec2 r4, r4, r16`
+
+ for i in range(0, VL):
+ # RA==RT in the instruction. does not have to be
+ iregs[RT].x = op(iregs[RT].x, iregs[RB+i].x)
+ iregs[RT].y = op(iregs[RT].y, iregs[RB+i].y)
+
+Thus logically there is nothing special or unanticipated about
+`SVM=0`: it is expected behaviour according to standard SVP64
+Sub-Vector rules.
+
+By contrast, when SVM is set and SUBVL!=1, a Horizontal
+Subvector mode is enabled, which behaves very much more
+like a traditional Vector Processor Reduction instruction.
+Example for a vec3:
for i in range(VL):
- result = op(iregs[RA+i].x, iregs[RA+i].x)
+ result = iregs[RA+i].x
result = op(result, iregs[RA+i].y)
result = op(result, iregs[RA+i].z)
iregs[RT+i] = result
-In this mode, when Rc=1 the Vector of CRs is as normal: each result element creates a corresponding CR element.
+In this mode, when Rc=1 the Vector of CRs is as normal: each result
+element creates a corresponding CR element (for the final, reduced, result).
# Fail-on-first
-Data-dependent fail-on-first has two distinct variants: one for LD/ST,
-the other for arithmetic operations (actually, CR-driven). Note in each
+Data-dependent fail-on-first has two distinct variants: one for LD/ST
+(see [[sv/ldst]],
+the other for arithmetic operations (actually, CR-driven)
+([[sv/normal]]) and CR operations ([[sv/cr_ops]]).
+Note in each
case the assumption is that vector elements are required appear to be
executed in sequential Program Order, element 0 being the first.
CR-creating operation produces a result (including cmp). Similar to
branch, an analysis of the CR is performed and if the test fails, the
vector operation terminates and discards all element operations at and
- above the current one, and VL is truncated to the *previous* element.
- Thus the new VL comprises a contiguous vector of results, all of which
- pass the testing criteria (equal to zero, less than zero).
-
-The CR-based data-driven fail-on-first is new and not found in ARM SVE
-or RVV. It is extremely useful for reducing instruction count, however
-requires speculative execution involving modifications of VL to get high
-performance implementations. An additional mode (RC1=1) effectively turns what would otherwise be an arithmetic operation into a type of `cmp`. The CR is stored (and the CR.eq bit tested). If the CR.eq bit fails then the Vector is truncated and the loop ends. Note that when RC1=1 the result elements arw never stored, only the CRs.
+ above the current one, and VL is truncated to either
+ the *previous* element or the current one, depending on whether
+ VLi (VL "inclusive") is set.
+
+Thus the new VL comprises a contiguous vector of results,
+all of which pass the testing criteria (equal to zero, less than zero).
+
+The CR-based data-driven fail-on-first is new and not found in ARM
+SVE or RVV. It is extremely useful for reducing instruction count,
+however requires speculative execution involving modifications of VL
+to get high performance implementations. An additional mode (RC1=1)
+effectively turns what would otherwise be an arithmetic operation
+into a type of `cmp`. The CR is stored (and the CR.eq bit tested
+against the `inv` field).
+If the CR.eq bit is equal to `inv` then the Vector is truncated and
+the loop ends.
+Note that when RC1=1 the result elements are never stored, only the CRs.
+
+VLi is only available as an option when `Rc=0` (or for instructions
+which do not have Rc). When set, the current element is always
+also included in the count (the new length that VL will be set to).
+This may be useful in combination with "inv" to truncate the Vector
+to `exclude` elements that fail a test, or, in the case of implementations
+of strncpy, to include the terminating zero.
In CR-based data-driven fail-on-first there is only the option to select
and test one bit of each CR (just as with branch BO). For more complex
vectorised operations are effectively `nops` which is
*precisely the desired and intended behaviour*.
-Another aspect is that for ffirst LD/STs, VL may be truncated arbitrarily to a nonzero value for any implementation-specific reason. For example: it is perfectly reasonable for implementations to alter VL when ffirst LD or ST operations are initiated on a nonaligned boundary, such that within a loop the subsequent iteration of that loop begins subsequent ffirst LD/ST operations on an aligned boundary. Likewise, to reduce workloads or balance resources.
+Another aspect is that for ffirst LD/STs, VL may be truncated arbitrarily
+to a nonzero value for any implementation-specific reason. For example:
+it is perfectly reasonable for implementations to alter VL when ffirst
+LD or ST operations are initiated on a nonaligned boundary, such that
+within a loop the subsequent iteration of that loop begins subsequent
+ffirst LD/ST operations on an aligned boundary. Likewise, to reduce
+workloads or balance resources.
-CR-based data-dependent first on the other hand MUST not truncate VL arbitrarily. This because it is a precise test on which algorithms will rely.
+CR-based data-dependent first on the other hand MUST not truncate VL
+arbitrarily to a length decided by the hardware: VL MUST only be
+truncated based explicitly on whether a test fails.
+This because it is a precise test on which algorithms
+will rely.
-# pred-result mode
+## Data-dependent fail-first on CR operations (crand etc)
-This mode merges common CR testing with predication, saving on instruction count. Below is the pseudocode excluding predicate zeroing and elwidth overrides.
+Operations that actually produce or alter CR Field as a result
+do not also in turn have an Rc=1 mode. However it makes no
+sense to try to test the 4 bits of a CR Field for being equal
+or not equal to zero. Moreover, the result is already in the
+form that is desired: it is a CR field. Therefore,
+CR-based operations have their own SVP64 Mode, described
+in [[sv/cr_ops]]
- for i in range(VL):
- # predication test, skip all masked out elements.
- if predicate_masked_out(i):
- continue
- result = op(iregs[RA+i], iregs[RB+i])
- CRnew = analyse(result) # calculates eq/lt/gt
- # Rc=1 always stores the CR
- if Rc=1 or RC1:
- crregs[offs+i] = CRnew
- # now test CR, similar to branch
- if RC1 or CRnew[BO[0:1]] != BO[2]:
- continue # test failed: cancel store
- # result optionally stored but CR always is
- iregs[RT+i] = result
+There are two primary different types of CR operations:
-The reason for allowing the CR element to be stored is so that post-analysis
-of the CR Vector may be carried out. For example: Saturation may have occurred (and been prevented from updating, by the test) but it is desirable to know *which* elements fail saturation.
+* Those which have a 3-bit operand field (referring to a CR Field)
+* Those which have a 5-bit operand (referring to a bit within the
+ whole 32-bit CR)
-Note that RC1 Mode basically turns all operations into `cmp`. The calculation is performed but it is only the CR that is written. The element result is *always* discarded, never written (just like `cmp`).
+More details can be found in [[sv/cr_ops]].
-Note that predication is still respected: predicate zeroing is slightly different: elements that fail the CR test *or* are masked out are zero'd.
+# pred-result mode
-## pred-result mode on CR ops
+Predicate-result merges common CR testing with predication, saving on
+instruction count. In essence, a Condition Register Field test
+is performed, and if it fails it is considered to have been
+*as if* the destination predicate bit was zero.
+Arithmetic and Logical Pred-result is covered in [[sv/normal]]
-Yes, really: CR operations (mtcr, crand, cror) may be Vectorised, predicated, and also pred-result mode applied to it. In this case, the Vectorisation applies to the batch of 4 bits, i.e. it is not the CR individual bits that are treated as the Vector, but the CRs themselves (CR0, CR8, CR9...)
+## pred-result mode on CR ops
-Thus after each Vectorised operation (crand) a test of the CR result can in fact be performed.
+CR operations (mtcr, crand, cror) may be Vectorised,
+predicated, and also pred-result mode applied to it.
+Vectorisation applies to 4-bit CR Fields which are treated as
+elements, not the individual bits of the 32-bit CR.
+CR ops and how to identify them is described in [[sv/cr_ops]]
# CR Operations
in BE format (*the relationship is not clearly explained in the v3.0B
or v3.1B specification*). However with some care and consideration
the exact same mapping used for INT and FP regfiles may be applied,
-just to the upper bits, as explained below.
-
-In OpenPOWER v3.0/1, BF/BT/BA/BB are all 5 bits. The top 3 bits (2:4)
-select one of the 8 CRs; the bottom 2 bits (0:1) select one of 4 bits
+just to the upper bits, as explained below. The notation
+`CR{field number}` is used to indicate access to a particular
+Condition Register Field (as opposed to the notation `CR[bit]`
+which accesses one bit of the 32 bit Power ISA v3.0B
+Condition Register)
+
+In OpenPOWER v3.0/1, BF/BT/BA/BB are all 5 bits. The top 3 bits (0:2)
+select one of the 8 CRs; the bottom 2 bits (3:4) select one of 4 bits
*in* that CR. The numbering was determined (after 4 months of
analysis and research) to be as follows:
CR_bit = (CR_reg & (1<<bit_index)) != 0
When it comes to applying SV, it is the CR\_reg number to which SV EXTRA2/3
-applies, **not** the CR\_bit portion (bits 0:1).
+applies, **not** the CR\_bit portion (bits 3:4):
if extra3_mode:
spec = EXTRA3
else:
spec = EXTRA2<<1 | 0b0
- # constructs "BA[2:4] spec[0:1] 00 BA[0:1]"
+ if spec[0]:
+ # vector constructs "BA[0:2] spec[1:2] 00 BA[3:4]"
return ((BA >> 2)<<6) | # hi 3 bits shifted up
- (spec[0:1]<<4) | # to make room for these
+ (spec[1:2]<<4) | # to make room for these
(BA & 0b11) # CR_bit on the end
+ else:
+ # scalar constructs "00 spec[1:2] BA[0:4]"
+ return (spec[1:2] << 5) | BA
Thus, for example, to access a given bit for a CR in SV mode, the v3.0B
-algorithm to determine CR\_reg is modified to as follows, noting that there are now 16 32 bit CRs, and that the element progression is *not linear*:
-
- def get_cr_bit(BA, idx): # for idx 0 to VL-1
- CR_index = 7-(BA>>2) # top 3 bits but BE
- CR_index = (CR_index<<4) | (spec[0:1] << 2)
- # first get one of the 16 32-bit CRs
- CR_row = (CR_index>>4) + (idx&0xf)
- CR = CRfile[CR_row]
- # now get the 4 bit CRn in that 32-bit CR
- CR_col = (CR_index + (idx>>4)) & 0x7
- CR_reg = CR{CR_col} # get 4 bit CRn
- # same as for v3.0/v3.1 from this point onwards
- bit_index = 3-(BA & 0b11) # low 2 bits but BE
- # finally get the bit from the CR.
- CR_bit = (CR_reg & (1<<bit_index)) != 0
+algorithm to determin CR\_reg is modified to as follows:
+
+ CR_index = 7-(BA>>2) # top 3 bits but BE
+ if spec[0]:
+ # vector mode, 0-124 increments of 4
+ CR_index = (CR_index<<4) | (spec[1:2] << 2)
+ else:
+ # scalar mode, 0-32 increments of 1
+ CR_index = (spec[1:2]<<3) | CR_index
+ # same as for v3.0/v3.1 from this point onwards
+ bit_index = 3-(BA & 0b11) # low 2 bits but BE
+ CR_reg = CR{CR_index} # get the CR
+ # finally get the bit from the CR.
+ CR_bit = (CR_reg & (1<<bit_index)) != 0
Note here that the decoding pattern to determine CR\_bit does not change.
Note: high-performance implementations may read/write Vectors of CRs in
-batches of aligned 32-bit chunks. This is to greatly
+batches of aligned 32-bit chunks (CR0-7, CR7-15). This is to greatly
simplify internal design. If instructions are issued where CR Vectors
do not start on a 32-bit aligned boundary, performance may be affected.
CR when Rc=1 is written to. This is CR0 for integer operations and CR1
for FP operations.
-Note that yes, the CRs are genuinely Vectorised. Unlike in SIMD VSX which
+Note that yes, the CR Fields are genuinely Vectorised. Unlike in SIMD VSX which
has a single CR (CR6) for a given SIMD result, SV Vectorised OpenPOWER
v3.0B scalar operations produce a **tuple** of element results: the
result of the operation as one part of that element *and a corresponding
If a "cumulated" CR based analysis of results is desired (a la VSX CR6)
then a followup instruction must be performed, setting "reduce" mode on
-the Vector of CRs, using cr ops (crand, crnor)to do so. This provides far
+the Vector of CRs, using cr ops (crand, crnor) to do so. This provides far
more flexibility in analysing vectors than standard Vector ISAs. Normal
Vector ISAs are typically restricted to "were all results nonzero" and
"were some results nonzero". The application of mapreduce to Vectorised
have the computation of the cumulative analysis CR as a bottleneck and
hindrance, regardless of the length of VL.
+Additionally,
+SVP64 [[sv/branches]] may be used, even when the branch itself is to
+the following instruction. The combined side-effects of CTR reduction
+and VL truncation provide several benefits.
+
(see [[discussion]]. some alternative schemes are described there)
## Rc=1 when SUBVL!=1
-sub-vectors are effectively a form of SIMD (length 2 to 4). Only 1 bit of predicate is allocated per subvector; likewise only one CR is allocated
+sub-vectors are effectively a form of Packed SIMD (length 2 to 4). Only 1 bit of
+predicate is allocated per subvector; likewise only one CR is allocated
per subvector.
-This leaves a conundrum as to how to apply CR computation per subvector, when normally Rc=1 is exclusively applied to scalar elements. A solution is to perform a bitwise OR or AND of the subvector tests. Given that OE is ignored, rhis field may (when available) be used to select OR or AND behavior.
+This leaves a conundrum as to how to apply CR computation per subvector,
+when normally Rc=1 is exclusively applied to scalar elements. A solution
+is to perform a bitwise OR or AND of the subvector tests. Given that
+OE is ignored in SVP64, this field may (when available) be used to select OR or
+AND behavior.
### Table of CR fields
CRs are not stored in SPRs: they are registers in their own right.
Therefore context-switching the full set of CRs involves a Vectorised
-mfcr or mtcr, using VL=64, elwidth=8 to do so. This is exactly as how scalar OpenPOWER context-switches CRs: it is just that there are now more of them.
+mfcr or mtcr, using VL=64, elwidth=8 to do so. This is exactly as how
+scalar OpenPOWER context-switches CRs: it is just that there are now
+more of them.
The 64 SV CRs are arranged similarly to the way the 128 integer registers
are arranged. TODO a python program that auto-generates a CSV file
## Single-predicated Instruction
-illustration of normal mode add operation: zeroing not included, elwidth overrides not included. if there is no predicate, it is set to all 1s
+illustration of normal mode add operation: zeroing not included, elwidth
+overrides not included. if there is no predicate, it is set to all 1s
function op_add(rd, rs1, rs2) # add not VADD!
- int i, id=0, irs1=0, irs2=0;
- predval = get_pred_val(FALSE, rd);
+ int i, id=0, irs1=0, irs2=0; predval = get_pred_val(FALSE, rd);
for (i = 0; i < VL; i++)
- STATE.srcoffs = i # save context
- if (predval & 1<<i) # predication uses intregs
- ireg[rd+id] <= ireg[rs1+irs1] + ireg[rs2+irs2];
- if (!int_vec[rd ].isvec) break;
- if (rd.isvec) { id += 1; }
- if (rs1.isvec) { irs1 += 1; }
- if (rs2.isvec) { irs2 += 1; }
- if (id == VL or irs1 == VL or irs2 == VL) {
- # end VL hardware loop
- STATE.srcoffs = 0; # reset
- return;
+ STATE.srcoffs = i # save context if (predval & 1<<i) # predication
+ uses intregs
+ ireg[rd+id] <= ireg[rs1+irs1] + ireg[rs2+irs2]; if (!int_vec[rd
+ ].isvec) break;
+ if (rd.isvec) { id += 1; } if (rs1.isvec) { irs1 += 1; } if
+ (rs2.isvec) { irs2 += 1; } if (id == VL or irs1 == VL or irs2 ==
+ VL) {
+ # end VL hardware loop STATE.srcoffs = 0; # reset return;
}
This has several modes:
-* RT.v = RA.v RB.v
-* RT.v = RA.v RB.s (and RA.s RB.v)
-* RT.v = RA.s RB.s
-* RT.s = RA.v RB.v
-* RT.s = RA.v RB.s (and RA.s RB.v)
-* RT.s = RA.s RB.s
+* RT.v = RA.v RB.v * RT.v = RA.v RB.s (and RA.s RB.v) * RT.v = RA.s RB.s *
+RT.s = RA.v RB.v * RT.s = RA.v RB.s (and RA.s RB.v) * RT.s = RA.s RB.s
-All of these may be predicated. Vector-Vector is straightfoward. When one of source is a Vector and the other a Scalar, it is clear that each element of the Vector source should be added to the Scalar source, each result placed into the Vector (or, if the destination is a scalar, only the first nonpredicated result).
+All of these may be predicated. Vector-Vector is straightfoward.
+When one of source is a Vector and the other a Scalar, it is clear that
+each element of the Vector source should be added to the Scalar source,
+each result placed into the Vector (or, if the destination is a scalar,
+only the first nonpredicated result).
-The one that is not obvious is RT=vector but both RA/RB=scalar. Here this acts as a "splat scalar result", copying the same result into all nonpredicated result elements. If a fixed destination scalar was intended, then an all-Scalar operation should be used.
+The one that is not obvious is RT=vector but both RA/RB=scalar.
+Here this acts as a "splat scalar result", copying the same result into
+all nonpredicated result elements. If a fixed destination scalar was
+intended, then an all-Scalar operation should be used.
See <https://bugs.libre-soc.org/show_bug.cgi?id=552>
* spred={reg spec}
similar to x86 "rex" prefix.
+
+For actual assembler:
+
+ sv.asmcode/mode.vec{N}.ew=8,sw=16,m={pred},sm={pred} reg.v, src.s
+
+Qualifiers:
+
+* m={pred}: predicate mask mode
+* sm={pred}: source-predicate mask mode (only allowed in Twin-predication)
+* vec{N}: vec2 OR vec3 OR vec4 - sets SUBVL=2/3/4
+* ew={N}: ew=8/16/32 - sets elwidth override
+* sw={N}: sw=8/16/32 - sets source elwidth override
+* ff={xx}: see fail-first mode
+* pr={xx}: see predicate-result mode
+* sat{x}: satu / sats - see saturation mode
+* mr: see map-reduce mode
+* mr.svm see map-reduce with sub-vector mode
+* crm: see map-reduce CR mode
+* crm.svm see map-reduce CR with sub-vector mode
+* sz: predication with source-zeroing
+* dz: predication with dest-zeroing
+
+For modes:
+
+* pred-result:
+ - pm=lt/gt/le/ge/eq/ne/so/ns OR
+ - pm=RC1 OR pm=~RC1
+* fail-first
+ - ff=lt/gt/le/ge/eq/ne/so/ns OR
+ - ff=RC1 OR ff=~RC1
+* saturation:
+ - sats
+ - satu
+* map-reduce:
+ - mr OR crm: "normal" map-reduce mode or CR-mode.
+ - mr.svm OR crm.svm: when vec2/3/4 set, sub-vector mapreduce is enabled
+
+# Proposed Parallel-reduction algorithm
+
+```
+/// reference implementation of proposed SimpleV reduction semantics.
+///
+ // reduction operation -- we still use this algorithm even
+ // if the reduction operation isn't associative or
+ // commutative.
+/// `temp_pred` is a user-visible Vector Condition register
+///
+/// all input arrays have length `vl`
+def reduce( vl, vec, pred, pred,):
+ step = 1;
+ while step < vl
+ step *= 2;
+ for i in (0..vl).step_by(step)
+ other = i + step / 2;
+ other_pred = other < vl && pred[other];
+ if pred[i] && other_pred
+ vec[i] += vec[other];
+ else if other_pred
+ vec[i] = vec[other];
+ pred[i] |= other_pred;
+
+def reduce( vl, vec, pred, pred,):
+ j = 0
+ vi = [] # array of lookup indices to skip nonpredicated
+ for i, pbit in enumerate(pred):
+ if pbit:
+ vi[j] = i
+ j += 1
+ step = 2
+ while step <= vl
+ halfstep = step // 2
+ for i in (0..vl).step_by(step)
+ other = vi[i + halfstep]
+ i = vi[i]
+ other_pred = other < vl && pred[other]
+ if pred[i] && other_pred
+ vec[i] += vec[other]
+ pred[i] |= other_pred
+ step *= 2
+
+```
projects / libreriscv.git / blobdiff