(no commit message)

[libreriscv.git] / openpower / sv / svp64 / appendix.mdwn

diff --git a/openpower/sv/svp64/appendix.mdwn b/openpower/sv/svp64/appendix.mdwn
index 2b55a509b8d20d5868a7bd0f738113415949887f..bad606195af4b8d3cfba31a94e8e7d9aa398c053 100644 (file)
--- a/openpower/sv/svp64/appendix.mdwn
+++ b/openpower/sv/svp64/appendix.mdwn
@@ -427,8 +427,9 @@ executed in sequential Program Order, element 0 being the first.
 * Data-driven (CR-driven) fail-on-first activates when Rc=1 or other
   CR-creating operation produces a result (including cmp).  Similar to
   branch, an analysis of the CR is performed and if the test fails, the
-  vector operation terminates and discards all element operations at and
-  above the current one, and VL is truncated to either
+  vector operation terminates and discards all element operations
+  above the current one (and the current one if VLi is not set),
+  and VL is truncated to either
   the *previous* element or the current one, depending on whether
   VLi (VL "inclusive") is set.
 
@@ -790,6 +791,10 @@ For modes:
 
 # Proposed Parallel-reduction algorithm
 
+**This algorithm contains a MV operation and may NOT be used.  Removal
+of the MV operation may be achieved by using index-redirection as was
+achieved in DCT and FFT REMAP**
+
 ```
 /// reference implementation of proposed SimpleV reduction semantics.
 ///
@@ -809,7 +814,9 @@ def reduce(vl, vec, pred):
             if pred[i] && other_pred
                 vec[i] += vec[other];
             else if other_pred
-                vec[i] = vec[other];
+                XXX VIOLATION OF SVP64 DESIGN XXX
+                XXX vec[i] = vec[other];      XXX
+                XXX VIOLATION OF SVP64 DESIGN XXX
             pred[i] |= other_pred;
 ```