`llvm.masked.compressstore.*`
followed by
`llvm.masked.expandload.*`
+with a single instruction.
+
+This extreme power and flexibility comes down to the fact that SVP64
+is not actually a Vector ISA: it is a loop-abstraction-concept that
+is applied *in general* to Scalar operations, just like the x86
+`REP` instruction (if put on steroids).
# Reduce modes
Looping which would terminate if the destination was marked as a Scalar.
Scalar Reduction by contrast *keeps issuing Vector Element Operations*
even though the destination register is marked as scalar.
-Thus it is up to the programmer to be aware of this and observe some
-conventions.
+Thus it is up to the programmer to be aware of this, observe some
+conventions, and thus end up achieving the desired outcome of scalar
+reduction.
It is also important to appreciate that there is no
actual imposition or restriction on how this mode is utilised: there
of different offsets masks and values to be inserted has multiple
applications including Video, cryptography and JIT compilation.
+Due to the Deterministic Scheduling,
Subtract and Divide are still permitted to be executed in this mode,
although from an algorithmic perspective it is strongly discouraged.
It would be better to use addition followed by one final subtract,
* Data-driven (CR-driven) fail-on-first activates when Rc=1 or other
CR-creating operation produces a result (including cmp). Similar to
branch, an analysis of the CR is performed and if the test fails, the
- vector operation terminates and discards all element operations at and
- above the current one, and VL is truncated to either
+ vector operation terminates and discards all element operations
+ above the current one (and the current one if VLi is not set),
+ and VL is truncated to either
the *previous* element or the current one, depending on whether
VLi (VL "inclusive") is set.
# Proposed Parallel-reduction algorithm
+**This algorithm contains a MV operation and may NOT be used. Removal
+of the MV operation may be achieved by using index-redirection as was
+achieved in DCT and FFT REMAP**
+
```
/// reference implementation of proposed SimpleV reduction semantics.
///
if pred[i] && other_pred
vec[i] += vec[other];
else if other_pred
- vec[i] = vec[other];
+ XXX VIOLATION OF SVP64 DESIGN XXX
+ XXX vec[i] = vec[other]; XXX
+ XXX VIOLATION OF SVP64 DESIGN XXX
pred[i] |= other_pred;
```