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[libreriscv.git]
/
openpower
/
sv
/
svp64
/
appendix.mdwn
diff --git
a/openpower/sv/svp64/appendix.mdwn
b/openpower/sv/svp64/appendix.mdwn
index 742d10feb4abb1565d8958e8ed13e8fd3704af57..bad606195af4b8d3cfba31a94e8e7d9aa398c053 100644
(file)
--- a/
openpower/sv/svp64/appendix.mdwn
+++ b/
openpower/sv/svp64/appendix.mdwn
@@
-814,7
+814,9
@@
def reduce(vl, vec, pred):
if pred[i] && other_pred
vec[i] += vec[other];
else if other_pred
- vec[i] = vec[other];
+ XXX VIOLATION OF SVP64 DESIGN XXX
+ XXX vec[i] = vec[other]; XXX
+ XXX VIOLATION OF SVP64 DESIGN XXX
pred[i] |= other_pred;
```