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[libreriscv.git] / openpower / sv / svp64 / appendix.mdwn

diff --git a/openpower/sv/svp64/appendix.mdwn b/openpower/sv/svp64/appendix.mdwn
index b402f41a00b493bc105903455e87082e3f44eb94..bfbae889afeda5af7303df75e02b4eb1f416a95c 100644 (file)
--- a/openpower/sv/svp64/appendix.mdwn
+++ b/openpower/sv/svp64/appendix.mdwn
@@ -145,7 +145,26 @@ there are only 9 bits available.
 Thirdly, a packing format was decided: for 2R-1W an EXTRA3 indexing
 could have been decided
 that RA would be indexed 0 (EXTRA bits 0-2), RB indexed 1 (EXTRA bits 3-5)
-and RT indexed 2 (EXTRA bits 6-8).
+and RT indexed 2 (EXTRA bits 6-8).  In some cases (LD/ST with update)
+RA-as-a-source is given a **different** EXTRA index from RA-as-a-result
+(because it is possible to do, and perceived to be useful).
+
+Fourthly, the instruction was analysed to see if Twin or Single
+Predication was suitable.  As a general rule this was if there
+was only a single operand and a single result (`extw` and LD/ST)
+however some 2 or 3 operand instructions also qualify.
+
+Fifthly, in an automated process the results of the analysis
+were outputted in CSV Format for use in machine-readable form
+by sv_analysis.py <https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=src/openpower/sv/sv_analysis.py;hb=HEAD>
+
+Quslifying future Power ISA Scalar instructions for SVP64
+is **strongly** advised to utilise this same process and the same
+sv_analysis.py program.  Alterations to that same program which
+change the Designation is **prohibited** once finalised (ratified
+through the Power ISA WG Process). It would
+be similar to deciding that `add` should be changed from X-Form
+to D-Form.
 
 # Single Predication