* **DRAFT STATUS v0.1 18sep2021** Release notes <https://bugs.libre-soc.org/show_bug.cgi?id=699>
-This document describes [[SV|sv]] augmentation of the [[OpenPOWER|openpower]] v3.0B [[ISA|openpower/isa/]]. Permission to create commercial v3.1 implementations has not yet been granted through the issuance of a v3.1 EULA by the [[!wikipedia OpenPOWER_Foundation]] (only v3.0B)
+This document describes [[SV|sv]] augmentation of the [[OpenPOWER|openpower]] v3.0B [[ISA|openpower/isa/]]. It is in Draft Status and
+will be submitted to the [[!wikipedia OpenPOWER_Foundation]] ISA WG
+via the External RFC Process.
Credits and acknowledgements:
This document focuses on the encoding of [[SV|sv]], and assumes familiarity with the same. It does not cover how SV works (merely the instruction encoding), and is therefore best read in conjunction with the [[sv/overview]].
-The plan is to create an encoding for SVP64, then to create an encoding
-for SVP48, then to reorganize them both to improve field overlap,
-reducing the amount of decoder hardware necessary.
-
All bit numbers are in MSB0 form (the bits are numbered from 0 at the MSB
and counting up as you move to the LSB end). All bit ranges are inclusive
(so `4:6` means bits 4, 5, and 6).
svp64 fits into the "reserved" portions of the v3.1 prefix, making it possible for svp64, v3.0B (or v3.1 including 64 bit prefixed) instructions to co-exist in the same binary without conflict.
+Subset implementations in hardware are permitted, as long as certain
+rules are followed, allowing for full soft-emulation including future
+revisions. Details in the [[svp64/appendix]].
+
## SVP64 encoding features
A number of features need to be compacted into a very small space of only 24 bits:
For the new fields added in SVP64, instructions that have any of their
fields set to a reserved value must cause an illegal instruction trap,
-to allow emulation of future instruction sets. Unless otherwise stated, reserved values are always all zeros.
+to allow emulation of future instruction sets, or for subsets of SVP64
+to be implemented in hardware and the rest emulated.
+This includes SVP64 SPRs: reading or writing values which are not
+supported in hardware must also raise illegal instruction traps
+in order to allow emulation.
+Unless otherwise stated, reserved values are always all zeros.
This is unlike OpenPower ISA v3.1, which in many instances does not require a trap if reserved fields are nonzero. Where the standard OpenPOWER definition
is intended the red keyword `RESERVED` is used.
-# Identity Behaviour
+# Scalar Identity Behaviour
SVP64 is designed so that when the prefix is all zeros, and
VL=1, no effect or
influence occurs (no augmentation) such that all standard OpenPOWER
-v3.0/1B instructions covered by the prefix are "unaltered". This is termed `scalar identity behaviour` (based on the mathematical definition for "identity", as in, "identity matrix" or better "identity transformation").
+v3.0/v3 1 instructions covered by the prefix are "unaltered". This is termed `scalar identity behaviour` (based on the mathematical definition for "identity", as in, "identity matrix" or better "identity transformation").
Note that this is completely different from when VL=0. VL=0 turns all operations under its influence into `nops` (regardless of the prefix)
- whereas when VL=1 and the SV prefix is all zeros, the operation simply acts as if SV had not been applied at all to the instruction (an "identity operation").
-
-The significance of identity behaviour is that instructions added under svp64 to the 32 bit suffix are not only accessible to svp64: as long as implementors conform to identity behaviour (set the prefix to all zeros) they may use the instructions without needing to actually implement SV itself.
+ whereas when VL=1 and the SV prefix is all zeros, the operation simply acts as if SV had not been applied at all to the instruction (an "identity transformation").
# Register Naming and size
| Field Name | Field bits | Description |
|------------|------------|----------------------------------------|
-| Rdest\_EXTRA2 | `10:11` | extends Rdest (R\*\_EXTRA2 Encoding) |
+| Rdest\_EXTRA2 | `10:11` | extends Rdest (R\*\_EXTRA2 Encoding) |
| Rsrc1\_EXTRA2 | `12:13` | extends Rsrc1 (R\*\_EXTRA2 Encoding) |
| Rsrc2\_EXTRA2 | `14:15` | extends Rsrc2 (R\*\_EXTRA2 Encoding) |
| Rsrc3\_EXTRA2 | `16:17` | extends Rsrc3 (R\*\_EXTRA2 Encoding) |
-| reserved | `18` | reserved |
+| EXTRA2_MODE | `18` | used by `divmod2du` and `madded` for RS |
+
+These are for 3 operand in and either 1 or 2 out instructions.
+3-in 1-out includes `madd RT,RA,RB,RC`. (DRAFT) instructions
+such as `madded` have an implicit second destination, RS, the
+selection of which is determined by bit 18.
## RM-1P-2S1D
The register files are therefore extended:
-* INT is extended from r0-31 to 128
-* FP is extended from fp0-32 to 128
-* CR is extended from CR0-7 to CR0-127
+* INT is extended from r0-31 to r0-127
+* FP is extended from fp0-32 to fp0-fp127
+* CR Fields are extended from CR0-7 to CR0-127
In the following tables register numbers are constructed from the
standard v3.0B / v3.1B 32 bit register field (RA, FRA) and the EXTRA2
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